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1. 发明授权

US11489697B2 Transmission of data on a local bus 有权
公开(公告)号：US11489697B2
公开(公告)日：2022-11-01
申请号：US16694116
申请日：2019-11-25
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm
IPC分类号： H04L12/403 , H04L12/40 , H04L12/42
摘要： A method for operating a local bus, in particular a ring bus, including data bus participants, as well as a local bus master are described. The method comprises transmitting a first identifier of a cycle frame, the first identifier defining the beginning of the cycle frame; transmitting process data and management data over the local bus, the process data and management data being transmitted within the cycle frame, at least one isochronous data packet containing the process data being transmitted in a first time interval for the first identifier, and, if management data is transmitted within the cycle frame, this management data is transmitted separately from the process data.

2. 发明授权

US11442736B2 Determination of data bus subscribers of a local bus 有权
公开(公告)号：US11442736B2
公开(公告)日：2022-09-13
申请号：US16694585
申请日：2019-11-25
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm
IPC分类号： H04L12/40 , H04L12/403 , H04L12/42 , H04L12/423 , G06F9/54 , G06F9/38 , G06F9/445
摘要： A method is described for identifying communication-ready data bus subscribers connected to a local bus. The method comprises receiving, at a local bus master, at least one data packet transmitted via the local bus, wherein the at least one data packet received at the local bus master comprises an address of a communication-ready data bus subscriber among a plurality of communication-ready data bus subscribers in the local bus, wherein the communication-ready data bus subscriber is in a sequence of communication-ready data bus subscribers, and mapping of the received address by the local bus master to a relative position of the communication-ready data bus subscriber in the sequence of communication-ready data bus subscribers in the local bus. In addition, a local bus master of the local bus is described.

3. 发明授权

US11580040B2 Synchronized processing of process data and delayed transmission 有权
公开(公告)号：US11580040B2
公开(公告)日：2023-02-14
申请号：US16693761
申请日：2019-11-25
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm , Frank Quakernack , Hans-Herbert Kirste
IPC分类号： G06F13/16 , G06F13/374 , G06F13/38 , G06F13/40 , G06F13/42
摘要： A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

4. 发明授权

US11411767B2 Module unit for connecting a data bus subscriber 有权
公开(公告)号：US11411767B2
公开(公告)日：2022-08-09
申请号：US16693939
申请日：2019-11-25
申请人： WAGO VERWALTUNGSGESELLSCHAFT MBH
发明人： Daniel Jerolm , Hans-Herbert Kirste , Anton Lischewski , Frank Schadde
IPC分类号： H04L12/40 , H04L12/42 , H04L12/28 , H04L12/50
摘要： A module unit for connecting a data bus participant to a local bus. The module unit has a first input interface and a first output interface which can be connected to the local bus, a first data connection interface which can be connected to the data bus participant, and a first switch which is adapted so as to assume a first or a second switch state depending on a control input from the data bus participant, connect the first input interface to the first output interface in the first switch state, and connect the first data connection interface to the first output interface in the second switch state.

5. 发明授权

US11411710B2 Subscriber of a data network 有权
公开(公告)号：US11411710B2
公开(公告)日：2022-08-09
申请号：US17158777
申请日：2021-01-26
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm
IPC分类号： H04L7/00 , H04L12/40
摘要： A subscriber of a wired data network, in particular of a local bus system, having internal clock generator for generating a clock generator signal having a clock generator frequency for the subscriber, a receive circuit for receiving a serial receive data stream, a processing circuit for inputting parallel receive data and for outputting parallel transmit data, and a transmit circuit for transmitting a serial transmit data stream. The receive circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into the parallel receive data. The receive circuit has a synchronization unit for synchronizing the internal clock generator to the data clock frequency contained in the serial receive data stream. The synchronization unit is configured for detecting transitions in the received serial receive data stream and for controlling the clock generator frequency of the internal clock generator as a function of the detected transitions.

6. 发明授权

US10985941B2 Initialization of a local bus 有权
公开(公告)号：US10985941B2
公开(公告)日：2021-04-20
申请号：US16694465
申请日：2019-11-25
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm
IPC分类号： H04L12/28 , H04L12/403 , H04L12/40 , H04L12/423
摘要： A method is described for communicating with data bus subscribers connected to a local bus, in particular a ring bus, with a local bus master, the method comprising sending a first data packet from the local bus master to all data bus subscribers for counting communication-ready data bus subscribers in a sequence, wherein the first data packet has a first counter value that is read out from each of the communication-ready data bus subscribers is changed in order; and sending a plurality of second data packets from the local bus master to all data bus subscribers, wherein the number of second data packets is based on the first counter value and wherein each of the second data packets is assigned to one of the communication-ready data bus subscribers based on the respective relative position of the communication-ready data bus subscribers in the sequence.

7. 发明授权

US10795847B2 Coupler for an automation system 有权
公开(公告)号：US10795847B2
公开(公告)日：2020-10-06
申请号：US15933843
申请日：2018-03-23
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Frank Quakernack , Daniel Jerolm , Hans-Herbert Kirste
IPC分类号： G06F13/40 , G06F13/10 , G06F13/28 , G11C7/10
摘要： A coupler for an automation system for controlling a process, having a first interface for connection to a field bus for receiving a field bus message with process data of the process, a second interface for connection to a local bus for transmitting a local bus message, and a circuit implemented between the first interface and the second interface. The circuit has a non-clocked logic circuit comprising a number of hardware logic elements. The non-clocked logic circuit is equipped to change process data received through the first interface. The circuit is equipped to output the changed process data in the local bus message.

8. 发明授权

US09436212B2 Data bus part and method for synchronizing data bus parts 有权
标题翻译：数据总线部分和数据总线部件同步的方法
公开(公告)号：US09436212B2
公开(公告)日：2016-09-06
申请号：US14028590
申请日：2013-09-17
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A data bus part with a data bus interface which has a downstream data bus input for receiving data from a higher-order data bus (1), and a clock generator for generating an internal clock signal for the data bus part, is described. The data bus part has a synchronization unit to synchronize the clock generator with the clock signal of the higher-order data bus part, wherein the synchronization unit is configured to detect transitions in the downstream data stream received at the downstream data input, to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phasing of the internal clock signal in relation to the detected transitions.
摘要翻译：具有数据总线接口的数据总线部分具有用于从高阶数据总线（1）接收数据的下行数据总线输入和用于产生数据总线部分的内部时钟信号的时钟发生器。数据总线部分具有同步单元，用于使时钟发生器与高阶数据总线部分的时钟信号同步，其中同步单元被配置为检测在下游数据输入处接收的下游数据流中的转变，以调节内部时钟信号的频率取决于检测到的转换，并且相对于检测到的转换来设置内部时钟信号的定义的定相。

9. 发明授权

US11537549B2 Status signal output 有权
公开(公告)号：US11537549B2
公开(公告)日：2022-12-27
申请号：US16693779
申请日：2019-11-25
申请人： WAGO VERWALTUNGSGESELLSCHAFT MBH
发明人： Daniel Jerolm , Hans-Herbert Kirste , Frank Schadde , Gerald Huse
IPC分类号： G06F13/42 , G06F13/374 , H04L12/40 , H04L12/42
摘要： A data bus subscriber connected to a local bus, particularly a ring bus. The data bus subscriber has a status signal input for receiving a first status signal value from a downstream data bus subscriber or a terminator, a status signal output for providing a second status signal value to an upstream data bus subscriber or to a local bus master, wherein the data bus subscriber is adapted to provide the second status signal value based on a logical link of a communication readiness of the data bus subscriber and the first status signal value. The invention further relates to a corresponding method and a local bus.

10. 发明授权

US11296903B2 Master of a bus system 有权
公开(公告)号：US11296903B2
公开(公告)日：2022-04-05
申请号：US16805411
申请日：2020-02-28
申请人： WAGO Verwaltungsgesellschaft mbH
发明人： Daniel Jerolm , Frank Quakernack
IPC分类号： H04L12/40 , H04L69/324
摘要： A master of a bus system for process control with one slave and a bus. A transceiver circuit transmits and receives for process control by data packets. A channel has a receive memory area. The transceiver circuit is set up to write the receive data of a data packet received via the bus into the receive memory area. The channel has at least one selection circuit, an output of the selection circuit being connected to the transceiver circuit. The selection circuit has a first input for selecting initial data. The selection circuit has a second input, the second input being connected to the receive memory area, and the selection circuit is configured to select the transmit data from the initial data and/or the data written into the receive memory area and to output the transmitted data to the transceiver circuit for a data packet to be transmitted.

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