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1. 发明授权

US09780183B2 Semiconductor devices having work function metal films and tuning materials 有权
公开(公告)号：US09780183B2
公开(公告)日：2017-10-03
申请号：US14989154
申请日：2016-01-06
申请人： Wan-Don Kim , Oh-Seong Kwon , Hoon-Joo Na , Hyeok-Jun Son , Jae-Yeol Song , Sung-Kee Han , Sang-Jin Hyun
发明人： Wan-Don Kim , Oh-Seong Kwon , Hoon-Joo Na , Hyeok-Jun Son , Jae-Yeol Song , Sung-Kee Han , Sang-Jin Hyun
IPC分类号： H01L29/49 , H01L27/088 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/4966 , H01L21/823431 , H01L21/82345 , H01L21/823462 , H01L27/0886 , H01L29/42364 , H01L29/4238
摘要： A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

2. 发明申请

US20120319216A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20120319216A1
公开(公告)日：2012-12-20
申请号：US13517756
申请日：2012-06-14
申请人： Jae-Yeol Song , Jeong-Hee Han , Sang-Jin Hyun , Hyeok-Jun Son , Sung-Kee Han
发明人： Jae-Yeol Song , Jeong-Hee Han , Sang-Jin Hyun , Hyeok-Jun Son , Sung-Kee Han
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28185 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.
摘要翻译：可以通过包括提供具有伪栅极图案的衬底的方法来制造具有减小的漏电流和增加电容而不增加等效氧化物厚度（EOT）的半导体器件; 通过去除伪栅极图案形成栅极形成沟槽; 在所述栅极形成沟槽内形成堆叠的绝缘层，其中所述层叠绝缘层的形成包括形成第一高k电介质层，通过对所述第一高k电介质层进行热处理形成第二高k电介质层，在热处理之后，在第二高k电介质层上形成第三高k电介质层，第三高k电介质层的相对介电常数高于第二高k电介质层，介电常数为 40以上; 以及在所述栅极形成沟槽内形成栅电极。

3. 发明授权

US09048307B2 Method of manufacturing a semiconductor device having sequentially stacked high-k dielectric layers 有权
标题翻译：具有顺序堆叠的高k电介质层的半导体器件的制造方法
公开(公告)号：US09048307B2
公开(公告)日：2015-06-02
申请号：US13517756
申请日：2012-06-14
申请人： Jae-Yeol Song , Jeong-Hee Han , Sang-Jin Hyun , Hyeok-Jun Son , Sung-Kee Han
发明人： Jae-Yeol Song , Jeong-Hee Han , Sang-Jin Hyun , Hyeok-Jun Son , Sung-Kee Han
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28185 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.
摘要翻译：可以通过包括提供具有伪栅极图案的衬底的方法来制造具有减小的漏电流和增加电容而不增加等效氧化物厚度（EOT）的半导体器件; 通过去除伪栅极图案形成栅极形成沟槽; 在所述栅极形成沟槽内形成堆叠的绝缘层，其中所述层叠绝缘层的形成包括形成第一高k电介质层，通过对所述第一高k电介质层进行热处理形成第二高k电介质层，并且在热处理之后，在第二高k电介质层上形成第三高k电介质层，第三高k电介质层的相对介电常数高于第二高k电介质层，介电常数为 40以上; 以及在所述栅极形成沟槽内形成栅电极。

4. 发明授权

US09812448B2 Semiconductor devices and methods for fabricating the same 有权
公开(公告)号：US09812448B2
公开(公告)日：2017-11-07
申请号：US14963271
申请日：2015-12-09
申请人： Oh-Seong Kwon , Jin-Kyu Jang , Wan-Don Kim , Hoon-Joo Na , Sang-Jin Hyun
发明人： Oh-Seong Kwon , Jin-Kyu Jang , Wan-Don Kim , Hoon-Joo Na , Sang-Jin Hyun
IPC分类号： H01L27/088 , H01L21/28 , H01L29/49 , H01L29/66 , H01L27/02 , H01L27/11 , H01L29/51 , H01L29/78 , H01L29/165 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/28088 , H01L21/82345 , H01L27/0207 , H01L27/0886 , H01L27/1104 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.

5. 发明申请

US20160181412A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160181412A1
公开(公告)日：2016-06-23
申请号：US14963271
申请日：2015-12-09
申请人： Oh-Seong Kwon , Jin-Kyu Jang , Wan-Don Kim , Hoon-Joo Na , Sang-Jin Hyun
发明人： Oh-Seong Kwon , Jin-Kyu Jang , Wan-Don Kim , Hoon-Joo Na , Sang-Jin Hyun
IPC分类号： H01L29/78 , H01L29/06 , H01L27/088
CPC分类号： H01L27/088 , H01L21/28088 , H01L21/82345 , H01L27/0207 , H01L27/0886 , H01L27/1104 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.
摘要翻译：提供了一种半导体器件，其被配置为通过在阻挡层之间形成氧化物层来阻挡物理扩散路径，以防止杂质通过阻挡层之间的物理扩散路径扩散，以及制造半导体器件的方法。半导体器件包括：形成在基板上的栅极绝缘层，形成在栅极绝缘层上的第一势垒层，形成在第一势垒层上的氧化物层，氧化物层包括通过氧化包含在第一势垒中的材料形成的氧化物形成在氧化物层上的第二阻挡层，形成在第二阻挡层上的栅电极和设置在基板中的栅电极的相对侧的源极/漏极。

6. 发明申请

US20120329262A1 METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES 有权
标题翻译：使用蚀刻介质层和相关器件制造半导体器件的方法
公开(公告)号：US20120329262A1
公开(公告)日：2012-12-27
申请号：US13528068
申请日：2012-06-20
申请人： Hoon-Joo NA , Hyung-Seok Hong , Sang-Bom Kang , Hyeok-Jun Son , June-Hee Lee , Jeong-Hee Han , Sang-Jin Hyun
发明人： Hoon-Joo NA , Hyung-Seok Hong , Sang-Bom Kang , Hyeok-Jun Son , June-Hee Lee , Jeong-Hee Han , Sang-Jin Hyun
IPC分类号： H01L21/8238
CPC分类号： H01L29/4958 , H01L21/82345 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L27/0928 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.
摘要翻译：制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层塞子。

7. 发明申请

US20120196433A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120196433A1
公开(公告)日：2012-08-02
申请号：US13208978
申请日：2011-08-12
申请人： Jeong-Hee Han , Hyeok-Jun Son , Sang-Jin Hyun , Hoon-Joo Na
发明人： Jeong-Hee Han , Hyeok-Jun Son , Sang-Jin Hyun , Hoon-Joo Na
IPC分类号： H01L21/28 , H01L21/311 , H01L21/263
CPC分类号： H01L21/02332 , H01L21/02238 , H01L21/02307 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/31111 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.
摘要翻译：提供一种半导体器件的制造方法，其具有减小的漏电流和增加的电容，同时改善界面特性。该制造方法包括在包括硅的基底层上形成氧化硅层，通过在氧化硅层中注入氮而形成氮氧化硅层，以及在蚀刻氮氧化硅层的同时在氧氮化硅层的表面上形成羟基。

8. 发明授权

US08748251B2 Methods for manufacturing semiconductor devices using etch stop dielectric layers and related devices 有权
标题翻译：使用蚀刻停止介质层和相关器件制造半导体器件的方法
公开(公告)号：US08748251B2
公开(公告)日：2014-06-10
申请号：US13528068
申请日：2012-06-20
申请人： Hoon-Joo Na , Hyung-Seok Hong , Sang-Bom Kang , Hyeok-Jun Son , June-Hee Lee , Jeong-Hee Han , Sang-Jin Hyun
发明人： Hoon-Joo Na , Hyung-Seok Hong , Sang-Bom Kang , Hyeok-Jun Son , June-Hee Lee , Jeong-Hee Han , Sang-Jin Hyun
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L29/4958 , H01L21/82345 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L27/0928 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.
摘要翻译：制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层塞子。

9. 发明授权

US09337057B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09337057B2
公开(公告)日：2016-05-10
申请号：US14802467
申请日：2015-07-17
申请人： Moon-Kyu Park , Oh-Seong Kwon , Sung-Kee Han , Sang-Jin Hyun
发明人： Moon-Kyu Park , Oh-Seong Kwon , Sung-Kee Han , Sang-Jin Hyun
IPC分类号： H01L21/3215 , H01L29/40 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/3105 , H01L21/823842 , H01L27/092 , H01L29/517 , H01L29/66545
摘要： Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.
摘要翻译：提供制造半导体器件的方法。制造半导体器件的方法可以包括在衬底上形成包括沟槽的第一层间绝缘膜，沿着沟槽的内侧壁和底表面形成高k层，形成包含杂质的第一功函数控制膜高k层，从第一功函数控制膜去除杂质，以使第一功函数控制膜的表面电阻降低约30％至约60％，并在沟槽中形成栅极金属。

10. 发明申请

US20110180879A1 CMOS TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND SEMICONDUCTOR MODULE INCLUDING THE DEVICE 有权
标题翻译： CMOS晶体管，包括晶体管的半导体器件和包括器件的半导体器件
公开(公告)号：US20110180879A1
公开(公告)日：2011-07-28
申请号：US12972961
申请日：2010-12-20
申请人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L23/522 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/82385 , H01L21/823871 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L27/0811 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
摘要翻译：提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。半导体衬底的第一和第二区域可以具有不同的导电类型。第一和第二互连结构可以设置在半导体衬底上。第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。半导体器件可以设置在半导体模块中。

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