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1. 发明授权

US08885383B1 Flash memory and layout method thereof 有权
标题翻译：闪存及其布局方法
公开(公告)号：US08885383B1
公开(公告)日：2014-11-11
申请号：US14037844
申请日：2013-09-26
申请人： Winbond Electronics Corp.
发明人： Jun-Lin Yeh , Ting-Kuo Yen
IPC分类号： G11C5/06 , G11C5/02 , H01L23/52 , G11C16/26 , H01L21/768
CPC分类号： H01L21/768 , G11C5/025 , G11C5/063 , G11C16/26 , G11C16/30
摘要： A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.
摘要翻译：公开了闪存。核心阵列存储数据。外围电路访问存储在核心阵列中的数据以产生读取数据。片外驱动器（OCD）处理读取的数据以产生输出数据。互连结构电连接到芯阵列，外围电路和OCD，并且包括三个导电层。导电层彼此电连接。在互连结构上形成最上层的导电层，电连接到互连结构，并且包括第一电源焊盘和第一电力轨道。第一功率垫通过第一接合线电连接到电源引脚以接收工作电压。第一电源轨道电连接在第一电源焊盘和互连结构之间，以将操作电压传输到芯阵列，外围电路和OCD中的至少一个。

2. 发明授权

US10978111B1 Sense amplifier circuit with reference voltage holding circuit for maintaining sense amplifier reference voltage when the sense amplifier operates under standby mode 有权
公开(公告)号：US10978111B1
公开(公告)日：2021-04-13
申请号：US16705147
申请日：2019-12-05
申请人： Winbond Electronics Corp.
发明人： Poongyeub Lee , Ting-Kuo Yen
IPC分类号： G11C7/14 , G11C7/06 , G11C5/14 , G11C16/26 , G11C16/28
摘要： In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.

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