专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090225616A1 MEMORY THAT RETAINS DATA WHEN SWITCHING PARTIAL ARRAY SELF REFRESH SETTINGS 有权
标题翻译：当切换部分阵列自刷新设置时保留数据的内存
公开(公告)号：US20090225616A1
公开(公告)日：2009-09-10
申请号：US12042785
申请日：2008-03-05
申请人： Wolfgang Hokenmaier , Farrukh Aquil , Steffen Loeffler
发明人： Wolfgang Hokenmaier , Farrukh Aquil , Steffen Loeffler
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/40622
摘要： A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.
摘要翻译：包括存储器单元阵列和控制电路的存储器。控制电路被配置为控制部分阵列自刷新并且从一个部分阵列自刷新切换到另一个部分阵列自刷新。经由一个部分阵列自刷新刷新并通过另一部分阵列自刷新刷新的存储单元中的数据在从一个部分阵列自刷新到另一个部分阵列自刷新到之前的第一次切换之前被保留在存储器单元中第一个开关。

2. 发明授权

US07969807B2 Memory that retains data when switching partial array self refresh settings 有权
标题翻译：切换部分阵列自刷新设置时保留数据的内存
公开(公告)号：US07969807B2
公开(公告)日：2011-06-28
申请号：US12042785
申请日：2008-03-05
申请人： Wolfgang Hokenmaier , Farrukh Aquil , Steffen Loeffler
发明人： Wolfgang Hokenmaier , Farrukh Aquil , Steffen Loeffler
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/40622
摘要： A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.
摘要翻译：包括存储器单元阵列和控制电路的存储器。控制电路被配置为控制部分阵列自刷新并且从一个部分阵列自刷新切换到另一个部分阵列自刷新。经由一个部分阵列自刷新刷新并通过另一部分阵列自刷新刷新的存储单元中的数据在从一个部分阵列自刷新到另一个部分阵列自刷新到之前的第一次切换之前被保留在存储器单元中第一个开关。

3. 发明申请

US20090237972A1 MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS 有权
标题翻译：内存包括外围电路支持部分或所有多个存储容量的银行
公开(公告)号：US20090237972A1
公开(公告)日：2009-09-24
申请号：US12053913
申请日：2008-03-24
申请人： Steffen Loeffler , Wolfgang Hokenmaier
发明人： Steffen Loeffler , Wolfgang Hokenmaier
IPC分类号： G11C5/06 , G11C8/00
CPC分类号： G11C5/14
摘要： A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.
摘要翻译：一种存储器，包括配置成支持多组存储器单元的外围电路。外围电路包括被设置为将外围电路置于第一模式以支持多组存储器单元的一部分的开关，以及支持所有多组存储单元的第二模式。

4. 发明授权

US07894283B2 Integrated circuit including selectable address and data multiplexing mode 有权
标题翻译：集成电路包括可选地址和数据复用模式
公开(公告)号：US07894283B2
公开(公告)日：2011-02-22
申请号：US12188558
申请日：2008-08-08
申请人： Margaret Freebern , Wolfgang Hokenmaier , Donald Labrecque , Steffen Loeffler , Ralf Klein
发明人： Margaret Freebern , Wolfgang Hokenmaier , Donald Labrecque , Steffen Loeffler , Ralf Klein
IPC分类号： G11C11/00
CPC分类号： G11C5/066 , G11C7/1045 , G11C7/1075 , G11C8/06 , G11C11/408 , G11C11/4096
摘要： An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.
摘要翻译：集成电路包括存储器阵列，第一焊盘和第二焊盘。集成电路被配置为在第一模式和第二模式中操作。第一模式包括接收第一焊盘上的数据信号和第二焊盘上的地址信号以访问存储器阵列。第二模式包括在第一焊盘上接收复用的数据信号和地址信号以访问存储器阵列。

5. 发明授权

US07889589B2 Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells 有权
标题翻译：存储器包括用于支持多组存储单元的一部分或全部的外围电路
公开(公告)号：US07889589B2
公开(公告)日：2011-02-15
申请号：US12053913
申请日：2008-03-24
申请人： Steffen Loeffler , Wolfgang Hokenmaier
发明人： Steffen Loeffler , Wolfgang Hokenmaier
IPC分类号： G11C8/00
CPC分类号： G11C5/14
摘要： A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.
摘要翻译：一种存储器，包括配置成支持多组存储器单元的外围电路。外围电路包括被设置为将外围电路置于第一模式以支持多组存储器单元的一部分的开关，以及支持所有多组存储单元的第二模式。

6. 发明申请

US20100034038A1 INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE 有权
标题翻译：集成电路，包括可选地址和数据多路复用模式
公开(公告)号：US20100034038A1
公开(公告)日：2010-02-11
申请号：US12188558
申请日：2008-08-08
申请人： Margaret Freebern , Wolfgang Hokenmaier , Donald Labrecque , Steffen Loeffler , Ralf Klein
发明人： Margaret Freebern , Wolfgang Hokenmaier , Donald Labrecque , Steffen Loeffler , Ralf Klein
IPC分类号： G11C8/00 , G11C29/00
CPC分类号： G11C5/066 , G11C7/1045 , G11C7/1075 , G11C8/06 , G11C11/408 , G11C11/4096
摘要： An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.
摘要翻译：集成电路包括存储阵列，第一焊盘和第二焊盘。集成电路被配置为在第一模式和第二模式中操作。第一模式包括接收第一焊盘上的数据信号和第二焊盘上的地址信号以访问存储器阵列。第二模式包括在第一焊盘上接收复用的数据信号和地址信号以访问存储器阵列。

7. 发明申请

US20100080043A1 APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS 有权
标题翻译：用于动态检测，选择和去除泄漏解除电容器的设备
公开(公告)号：US20100080043A1
公开(公告)日：2010-04-01
申请号：US12239624
申请日：2008-09-26
申请人： Jochen Hoffmann , Steffen Loeffler
发明人： Jochen Hoffmann , Steffen Loeffler
IPC分类号： G11C11/24 , G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C2029/5002
摘要： Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal.
摘要翻译：本发明的实施例通常涉及集成电路中的去耦电容器阵列的布置。去耦电容器阵列可以包括彼此电耦合的多个位线，彼此电耦合的多个字线和多个去耦电容器，每个去耦电容器耦合到相应的位线和字线。去耦电容器阵列还可以包括电耦合到多个字线的接入电路和电网，所述接入电路被配置为基于控制信号将去耦电容器阵列连接或断开到电网。

8. 发明申请

US20090080582A1 METHOD AND APPARATUS FOR ADJUSTING THE TIMING OF AN ELECTRONIC CIRCUIT 失效
标题翻译：用于调整电子电路时序的方法和装置
公开(公告)号：US20090080582A1
公开(公告)日：2009-03-26
申请号：US11859273
申请日：2007-09-21
申请人： Steffen Loeffler , Jochen Hoffmann
发明人： Steffen Loeffler , Jochen Hoffmann
IPC分类号： H04L7/04
CPC分类号： G11C7/04 , G11C5/063 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/22
摘要： Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters.
摘要翻译：用于检测电子设备内的信号传播速率变化的方法和电路，以及响应于信号传播速率的变化来调整设备的输出定时。根据本发明的实施例，信号可以通过未补偿的延迟链和经补偿的延迟链传播。如果信号通过补偿链比通过未补偿的延迟链更慢，则器件可以延迟时钟信号，使得器件的输出定时将保持在规范参数内。相比之下，如果信号通过未补偿的延迟链比通过补偿的延迟链更慢，则器件可能不会延迟所接收的时钟信号，使得器件的输出定时将保持在规范参数内。

9. 发明申请

US20100079150A1 APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS 审中-公开
标题翻译：用于动态检测，选择和去除泄漏解除电容器的装置
公开(公告)号：US20100079150A1
公开(公告)日：2010-04-01
申请号：US12239575
申请日：2008-09-26
申请人： Jochen Hoffmann , Steffen Loeffler
发明人： Jochen Hoffmann , Steffen Loeffler
IPC分类号： G01R31/12 , G01R31/02
CPC分类号： G11C29/02 , G11C11/401 , G11C29/025 , G11C29/50008 , G11C2029/5006
摘要： Embodiments of the invention generally provide methods, systems, and apparatus for testing decoupling capacitors of an integrated circuit. A decoupling capacitor may be disconnected from the power grid of the integrated circuit during testing. The voltage of the decoupling capacitor may be compared to the voltage of a reference capacitor to determine whether the decoupling capacitor is defective. If the decoupling capacitor is determined to be defective, the decoupling capacitor is not reconnected to the power grid, thereby reducing the leakage currents in the integrated circuit.
摘要翻译：本发明的实施例通常提供用于测试集成电路的去耦电容器的方法，系统和装置。在测试期间，去耦电容器可能与集成电路的电网断开。可以将去耦电容器的电压与参考电容器的电压进行比较，以确定去耦电容器是否有缺陷。如果解耦电容被确定为有缺陷，则去耦电容器不会重新连接到电网，从而减少集成电路中的漏电流。

10. 发明申请

US20080266990A1 Flexible redundancy replacement scheme for semiconductor device 审中-公开
标题翻译：半导体器件的灵活冗余替换方案
公开(公告)号：US20080266990A1
公开(公告)日：2008-10-30
申请号：US11790934
申请日：2007-04-30
申请人： Steffen Loeffler
发明人： Steffen Loeffler
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block.
摘要翻译：一种冗余替换方案，用于修复包括存储单元的故障存储单元，所述存储单元布置在包含字线和列选择线的存储块中。冗余替换方案包括基于第一存储块的解码地址将第二存储器块中的有缺陷的存储单元替换为第二存储器块中的备用存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式