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1. 发明授权

US11461625B1 Tensor compression 有权
公开(公告)号：US11461625B1
公开(公告)日：2022-10-04
申请号：US16881612
申请日：2020-05-22
申请人： Xilinx, Inc.
发明人： Michael Wu , Christopher H. Dick
IPC分类号： G06N3/063 , H03M7/30 , G06F7/22 , G06F7/50 , G06F7/523
摘要： Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the inverse of the lossy compression. The compression circuit and decompression circuit have parallel multiplier circuits and parallel adder circuits to perform the lossy compression and lossy decompression, respectively.

2. 发明授权

US10263644B1 Hybrid architecture for LDPC channel coding in data center 有权
公开(公告)号：US10263644B1
公开(公告)日：2019-04-16
申请号：US14925825
申请日：2015-10-28
申请人： Xilinx, Inc.
发明人： Raied N. Mazahreh , Hai-Jo Tarn , Nihat E. Tunali , Christopher H. Dick
IPC分类号： H03M13/37 , H03M13/11 , G06F11/10
摘要： Methods and systems are presented in this disclosure for implementing forward error correction in cloud and data center storage devices based on low-density parity-check (LDPC) channel coding. A forward error correction circuit presented herein includes a first LDPC decoder configured to perform hard-decision LDPC decoding of data read from a storage medium through a first read channel. The forward error correction circuit further includes a hybrid LDPC decoder selectively configurable to perform a selected one of hard-decision LDPC decoding and soft-decision LDPC decoding of data read from the storage medium through a second read channel, wherein, responsive to a control signal generated based, at least in part, on one or more parameters indicative of condition of the storage medium, the hybrid LDPC decoder is switchable between hard-decision LDPC decoding and soft-decision LDPC decoding.

3. 发明授权

US09941943B1 Coordinate descent detector and precoder for multiple-input multiple-output (MIMO) system 有权
公开(公告)号：US09941943B1
公开(公告)日：2018-04-10
申请号：US15160847
申请日：2016-05-20
申请人： Xilinx, Inc.
发明人： Michael Wu , Christopher H. Dick , Christoph E. Studer
IPC分类号： H04B7/02 , H04B7/0456 , H04B7/0413 , H04L25/02
CPC分类号： H04L25/0242 , H04B7/0413
摘要： A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.

4. 发明授权

US09935604B2 Variable bandwidth filtering 有权
公开(公告)号：US09935604B2
公开(公告)日：2018-04-03
申请号：US14791852
申请日：2015-07-06
申请人： Xilinx, Inc.
发明人： Fredric J. Harris , Christopher H. Dick
IPC分类号： H03K9/10 , H04L27/22 , H03H7/12 , H03H17/02
CPC分类号： H03H7/12 , H03H17/0266
摘要： An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. A mask is coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output. A synthesis filter bank is coupled to the mask. The synthesis filter bank is configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth. The second bandwidth is different than the first bandwidth for the variable bandwidth filtering.

5. 发明授权

US09590567B2 Moving mean and magnitude dual path digital predistortion 有权
标题翻译：移动平均和幅度双路数字预失真
公开(公告)号：US09590567B2
公开(公告)日：2017-03-07
申请号：US14790364
申请日：2015-07-02
申请人： Xilinx, Inc.
发明人： Hongzhi Zhao , Christopher H. Dick
IPC分类号： H04K1/02 , H03F1/32 , H03F3/189 , H03F3/24 , H04B1/04
CPC分类号： H03F1/3247 , H03F1/3252 , H03F1/3258 , H03F3/189 , H03F3/195 , H03F3/24 , H03F3/245 , H03F2201/3209 , H03F2201/3215 , H03F2201/3224 , H03F2201/3233 , H04B1/0475 , H04B2001/0425
摘要： An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for receiving the input signal for providing a moving mean signal. The first digital predistortion module further includes a digital predistorter for receiving the input signal and the moving mean signal for providing the first predistorted signal.
摘要翻译：装置一般涉及预处理输入信号。在该装置中，第一数字预失真模块和第二数字预失真模块用于接收用于分别提供第一预失真信号和第二预失真信号的输入信号。组合器用于组合第一预失真信号和第二预失真信号以提供输出信号。第一数字预失真模块包括移动平均块，用于接收用于提供移动平均信号的输入信号。第一数字预失真模块还包括用于接收输入信号的数字预失真器和用于提供第一预失真信号的移动平均信号。

6. 发明申请

US20170004031A1 VARIABLE CODE RATE SOLID-STATE DRIVE 有权
标题翻译：可变代码速率固态驱动
公开(公告)号：US20170004031A1
公开(公告)日：2017-01-05
申请号：US14789017
申请日：2015-07-01
申请人： Xilinx, Inc.
发明人： Christopher H. Dick
IPC分类号： G06F11/10 , H03M13/11 , G11C29/52
CPC分类号： G06F11/1068 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/52 , H03M13/1102 , H03M13/1111 , H03M13/353 , H03M13/635 , H03M13/6393
摘要： An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.
摘要翻译：一种装置及其方法一般涉及管理固态存储器的可靠性。在这种装置中，存在用于提供码率的存储器控制器。编码器用于接收输入数据和用于提供编码数据的码率。固态存储器用于接收和存储编码数据。解码器用于访问存储在固态存储器中的编码数据，并且用于接收用于提供所访问的编码数据的解码数据的码率。解码数据作为表示解码数据概率的软决策提供。存储器控制器用于响应于解码数据的概率而接收用于调整码率的解码数据。

7. 发明授权

US09503301B2 Noise-shaping crest factor reduction with polyphase transforming 有权
标题翻译：通过多相变换降噪成形波峰因子
公开(公告)号：US09503301B2
公开(公告)日：2016-11-22
申请号：US14662099
申请日：2015-03-18
申请人： Xilinx, Inc.
发明人： Christopher H. Dick
IPC分类号： H04J3/02 , H04L27/26 , H04L1/00
CPC分类号： H04L27/2623 , H04B1/005 , H04L1/0009 , H04L5/001 , H04L27/2624 , H04L27/2631
摘要： Apparatus, system and method relates generally to data communication with noise-shaping crest factor reduction using polyphase transformation. In such a method, a composite signal is received by a delay and a waveform generator. The waveform generator is for noise-shaping crest factor reduction using polyphase transformation. The composite signal is delayed by the delay to provide a delayed composite signal. A waveform is generated by the waveform generator from the composite signal. The waveform is output from the waveform generator having clipping noise with respect to bands of corresponding carriers of the composite signal. The waveform is subtracted from the delayed version of the composite signal for peak-to-amplitude power ratio reduction. A reduced peak version of the delayed version of the composite signal delayed is output from the signal combiner.
摘要翻译：装置，系统和方法一般涉及使用多相变换的噪声整形波峰因数减少的数据通信。在这种方法中，通过延迟和波形发生器接收复合信号。波形发生器用于使用多相变换进行噪声整形波峰因数降低。复合信号被延迟延迟以提供延迟复合信号。由复合信号由波形发生器产生波形。该波形相对于复合信号的相应载波的频带从具有限幅噪声的波形发生器输出。从复合信号的延迟版本中减去峰值功率比降低波形。从信号组合器输出延迟的复合信号的延迟版本的降低峰值版本。

8. 发明授权

US09001924B1 Matrix inversion 有权
标题翻译：矩阵反演
公开(公告)号：US09001924B1
公开(公告)日：2015-04-07
申请号：US13757084
申请日：2013-02-01
申请人： Xilinx, Inc.
发明人： Michael Wu , Bei Yin , Aida Vosoughi , Christopher H. Dick , Christoph E. Studer , Joseph R. Cavallaro
IPC分类号： H04L27/00 , H04B7/04 , G06F17/16
CPC分类号： G06F17/16 , H04B7/0413
摘要： An apparatus relating generally to matrix inversion is disclosed. This apparatus includes a matrix inversion module coupled to receive matrix information and to provide an approximation of an inversion of the matrix information. The matrix inversion module comprises a decomposition block coupled to receive the matrix information and to decompose the matrix information into diagonal matrix information and off diagonal matrix information, and an expansion block. The expansion block is coupled to receive the diagonal matrix information and the off diagonal matrix information, and to invert a matrix sum of the diagonal matrix information and the off diagonal matrix information by generation of a portion of a series expansion.
摘要翻译：公开了一般涉及矩阵反演的装置。该装置包括耦合以接收矩阵信息并提供矩阵信息的反演的近似的矩阵反演模块。矩阵反演模块包括耦合以接收矩阵信息并将矩阵信息分解为对角矩阵信息和离散对角矩阵信息的分解块和扩展块。扩展块被耦合以接收对角矩阵信息和非对角矩阵信息，并且通过生成一系列扩展的一部分来反转对角矩阵信息和非对角矩阵信息的矩阵和。

9. 发明授权

US10747690B2 Device with data processing engine array 有权
公开(公告)号：US10747690B2
公开(公告)日：2020-08-18
申请号：US15944307
申请日：2018-04-03
申请人： Xilinx, Inc.
发明人： Goran H K Bilski , Juan J. Noguera Serra , Baris Ozgul , Jan Langer , Richard L. Walke , Ralph D. Wittig , Kornelis A. Vissers , Philip B. James-Roxby , Christopher H. Dick
IPC分类号： G06F15/78 , G06F13/16 , G06F13/40 , G06F15/173 , H04L12/933
摘要： A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

10. 发明申请

US20190303311A1 DEVICE WITH DATA PROCESSING ENGINE ARRAY 审中-公开
公开(公告)号：US20190303311A1
公开(公告)日：2019-10-03
申请号：US15944307
申请日：2018-04-03
申请人： Xilinx, Inc.
发明人： Goran HK Bilski , Juan J. Noguera Serra , Baris Ozgul , Jan Langer , Richard L. Walke , Ralph D. Wittig , Kornelis A. Vissers , Philip B. James-Roxby , Christopher H. Dick
IPC分类号： G06F13/16 , G06F13/40
摘要： A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

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