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1. 发明授权

US08881079B1 Dataflow parameter estimation for a design 有权
标题翻译：设计数据流参数估计
公开(公告)号：US08881079B1
公开(公告)日：2014-11-04
申请号：US13797771
申请日：2013-03-12
申请人： Xilinx, Inc.
发明人： Peichen Pan , Chang'an Ye , Kecheng Hao
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.
摘要翻译：公开了一种数据流管线的高级合成方法的实施例。该实施例包括从数据流管线的高级合成获得处理。确定用于进程的先入先出数据信道的读操作和写操作的调度。确定通过数据流管道的数据流进度表。生成用于进程和数据流的边缘加权有向非循环图。位于边缘加权有向非循环图中的最长路径。输出最长路径的权重作为估计，例如数据流的等待时间估计。

2. 发明授权

US11604758B2 Systems and methods for systolic array design from a high-level program 有权
公开(公告)号：US11604758B2
公开(公告)日：2023-03-14
申请号：US17096742
申请日：2020-11-12
申请人： Xilinx, Inc.
发明人： Peng Zhang , Cody Hao Yu , Xuechao Wei , Peichen Pan
IPC分类号： G06F9/30 , G06F15/80 , G06N3/08 , G06N3/04 , G06N3/063
摘要： Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.

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