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1. 发明授权

US07894273B2 Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits 有权
标题翻译：通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
公开(公告)号：US07894273B2
公开(公告)日：2011-02-22
申请号：US12407665
申请日：2009-03-19
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

2. 发明授权

US07768836B2 Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits 有权
标题翻译：通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
公开(公告)号：US07768836B2
公开(公告)日：2010-08-03
申请号：US12249678
申请日：2008-10-10
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

3. 发明申请

US20100091573A1 Nonvolatile Memory And Method With Reduced Program Verify By Ignoring Fastest And/Or Slowest Programming Bits 有权
标题翻译：通过忽略最快和/或最慢的编程位，减少程序验证的非易失性存储器和方法
公开(公告)号：US20100091573A1
公开(公告)日：2010-04-15
申请号：US12249678
申请日：2008-10-10
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

4. 发明授权

US08228741B2 Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits 有权
标题翻译：通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
公开(公告)号：US08228741B2
公开(公告)日：2012-07-24
申请号：US13029848
申请日：2011-02-17
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C11/36 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

5. 发明申请

US20100091568A1 Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest and/or Slowest Programming Bits 有权
标题翻译：通过忽略最快和/或最慢的编程位，减少程序验证的非易失性存储器和方法
公开(公告)号：US20100091568A1
公开(公告)日：2010-04-15
申请号：US12407665
申请日：2009-03-19
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

6. 发明申请

US20080065813A1 METHODS IN A PSEUDO RANDOM AND COMMAND DRIVEN BIT COMPENSATION FOR THE CYCLING EFFECTS IN FLASH MEMORY 有权
标题翻译：闪存中循环效应的PSEUDO随机和命令驱动位补偿方法
公开(公告)号：US20080065813A1
公开(公告)日：2008-03-13
申请号：US11530399
申请日：2006-09-08
申请人： Yan Li , Yupin Kawing Fong
发明人： Yan Li , Yupin Kawing Fong
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G11C16/3418
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

7. 发明授权

US07734861B2 Pseudo random and command driven bit compensation for the cycling effects in flash memory 有权
标题翻译：伪随机和命令驱动位补偿闪存中的循环效应
公开(公告)号：US07734861B2
公开(公告)日：2010-06-08
申请号：US11530392
申请日：2006-09-08
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G06F13/10
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5621 , G11C16/0483 , G11C16/3427
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

8. 发明授权

US07057939B2 Non-volatile memory and control with improved partial page program capability 有权
标题翻译：非易失性存储器和具有改进的部分页面编程能力的控制
公开(公告)号：US07057939B2
公开(公告)日：2006-06-06
申请号：US10830824
申请日：2004-04-23
申请人： Yan Li , Yupin Kawing Fong , Toru Miwa
发明人： Yan Li , Yupin Kawing Fong , Toru Miwa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.
摘要翻译：在非易失性存储器编程方案中，其中存储器单元被编程在两个或多个顺序编程遍中，当在第二遍期间存在不足的主机数据来编程至少一些存储器单元时，一些存储器单元可被编程到错误的阈值电压。这可以通过修改编程方案来避免这样的情况。在一个实现中，这是通过选择代码方案来实现的，该代码方案不会在第二编程遍期间将存储器单元编程到错误的阈值电压，或者通过根据不会导致单元被编程为错误状态。

9. 发明申请

US20110134703A1 Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest And/Or Slowest Programming Bits 有权
标题翻译：通过忽略最快和/或最慢的编程位，减少程序验证的非易失性存储器和方法
公开(公告)号：US20110134703A1
公开(公告)日：2011-06-09
申请号：US13029848
申请日：2011-02-17
申请人： Yan Li , Yupin Kawing Fong , Situ Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Situ Lung Chan
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

10. 发明授权

US07606966B2 Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory 有权
标题翻译：闪存中循环效应的伪随机和命令驱动位补偿方法
公开(公告)号：US07606966B2
公开(公告)日：2009-10-20
申请号：US11530399
申请日：2006-09-08
申请人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
发明人： Yan Li , Yupin Kawing Fong , Nima Mokhlesi
IPC分类号： G06F13/10
CPC分类号： G11C7/1006 , G11C16/3418
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

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