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1. 发明授权

US08468188B1 Movable tap finite impulse response filter 有权
标题翻译：可动抽头有限脉冲响应滤波器
公开(公告)号：US08468188B1
公开(公告)日：2013-06-18
申请号：US13012700
申请日：2011-01-24
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G06F17/10
CPC分类号： H03H17/0248 , H03H17/0009 , H03H17/06 , H04B3/23
摘要： A finite impulse response (FIR) filter apparatus including: an input configured to receive a first input signal; a plurality of coefficient taps configured to filter the first input signal; a plurality of delay elements arranged between the plurality of coefficient taps, the plurality of delay elements configured to delay the first input signal, wherein at least one of the plurality of delay elements is configured to provide a variable delay; and a processor configured to i) determine signal strengths of respective portions of the first input signal, and ii) in response to determining the signal strengths, set the variable delay to skip filtering selected portions of the first input signal.
摘要翻译：一种有限脉冲响应（FIR）滤波器装置，包括：被配置为接收第一输入信号的输入; 多个系数抽头，用于对第一输入信号进行滤波; 布置在所述多个系数抽头之间的多个延迟元件，所述多个延迟元件被配置为延迟所述第一输入信号，其中所述多个延迟元件中的至少一个被配置为提供可变延迟; 以及处理器，其被配置为i）确定所述第一输入信号的相应部分的信号强度，以及ii）响应于确定所述信号强度，设置所述可变延迟以跳过所述第一输入信号的所选部分。

2. 发明授权

US06369967B1 Phase-adjustment of divided clock in disk head read circuit 有权
标题翻译：磁头读取电路中分频时钟的相位调整
公开(公告)号：US06369967B1
公开(公告)日：2002-04-09
申请号：US09660929
申请日：2000-09-13
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G11B509
CPC分类号： G11B27/3027 , G11B5/012 , G11B20/1426 , G11B2220/20 , H03L7/06
摘要： A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.
摘要翻译：用于根据来自磁盘头的模拟数据向磁盘控制器提供多位磁盘数据的读取电路包括低频时钟发生器，其相位可响应于模拟磁盘数据中的同步标记的检测而可调节。高频时钟被锁定到磁盘头的输出端，并且使A / D转换器和位检测器的操作同步，该位检测器基于A / D输出产生经验证的单位。串行到并行转换器将位检测器的单位输出转换为并行输出，并行输出被锁存到多位磁盘数据，供磁盘控制器根据低频时钟使用。低频时钟由来自高频时钟的时钟发生器产生，具有响应于同步标记检测器可调节的相位。

3. 发明授权

US08180946B1 Long latency interface protocol 有权
标题翻译：长延时接口协议
公开(公告)号：US08180946B1
公开(公告)日：2012-05-15
申请号：US12876715
申请日：2010-09-07
申请人： Yat-Tung Lam , Pantas Sutardja
发明人： Yat-Tung Lam , Pantas Sutardja
IPC分类号： G06F13/14
CPC分类号： G11B20/14 , G06F13/00 , G06F13/14 , G11B5/09 , G11C29/00
摘要： An interface configured to support a signaling protocol between a first hardware component and a second hardware component. The interface comprises a first pin, a second pin, and a third pin. The first pin is configured to provide a write clock signal sourced from the first hardware component to the second hardware component during a write operation. The second pin is configured to receive a read clock signal sourced from the second hardware component during a read operation. The third pin is configured to transfer serial control information from the first hardware component to the second hardware component during both the read operation and the write operation. Only the third pin is used to transfer the serial control information. The serial control information includes control information for both the read operation and the write operation.
摘要翻译：被配置为支持第一硬件组件和第二硬件组件之间的信令协议的接口。接口包括第一引脚，第二引脚和第三引脚。第一引脚被配置为在写操作期间将来自第一硬件组件的写时钟信号提供给第二硬件组件。第二引脚被配置为在读操作期间接收来自第二硬件组件的读时钟信号。第三引脚被配置为在读操作和写操作期间将串行控制信息从第一硬件组件传送到第二硬件组件。只有第三个引脚用于传输串行控制信息。串行控制信息包括读取操作和写入操作两者的控制信息。

4. 发明授权

US07877429B1 Movable tap finite impulse response filter 有权
标题翻译：可动抽头有限脉冲响应滤波器
公开(公告)号：US07877429B1
公开(公告)日：2011-01-25
申请号：US11545356
申请日：2006-10-10
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G06F17/10
CPC分类号： H03H17/0248 , H03H17/0009 , H03H17/06 , H04B3/23
摘要： FIR filter apparatus comprises an input responsive to an input signal and an FIR filter that comprises three filter stages. A first delay circuit has a first time delay coupled between two of the three filter stages. A second delay circuit has a second time delay coupled between another two of the three filter stages. The first time delay and second time delay are different.
摘要翻译： FIR滤波器装置包括响应于输入信号的输入和包括三个滤波器级的FIR滤波器。第一延迟电路具有耦合在三个滤波器级中的两个之间的第一时间延迟。第二延迟电路具有耦合在三个滤波器级中的另外两个之间的第二时间延迟。第一次延迟和第二次延迟是不同的。

5. 发明授权

US07827224B1 Movable tap finite impulse response filter 有权
标题翻译：可动抽头有限脉冲响应滤波器
公开(公告)号：US07827224B1
公开(公告)日：2010-11-02
申请号：US11545204
申请日：2006-10-10
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G06F17/10
CPC分类号： H03H17/0248 , H03H17/0009 , H03H17/06 , H04B3/23
摘要： A method selects a period of delay in an FIR filter having (i) a plurality of delay elements and (ii) a plurality of coefficient taps each associated with a portion of an input signal in corresponding stages of delay from a corresponding delay element, in which at least one delay element has a period of delay that is selectable. The method includes measuring components of an input signal so as to identify a sequence of components that are smaller than another sequence of larger components. The method includes setting the selectable period of delay to prevent application of the identified sequence of smaller components of the input signal to the coefficient taps.
摘要翻译：一种方法选择具有（i）多个延迟元件和（ii）多个系数抽头的FIR滤波器中的延迟周期，每个系数抽头与来自相应的延迟元件的延迟相应的输入信号的一部分相关联，其中至少一个延迟元件具有可选择的延迟周期。该方法包括测量输入信号的分量，以便识别小于另一个较大分量序列的分量序列。该方法包括设置可选择的延迟周期以防止所识别的输入信号的较小分量的序列应用于系数抽头。

6. 发明授权

US07793028B1 Long latency interface protocol 有权
标题翻译：长延时接口协议
公开(公告)号：US07793028B1
公开(公告)日：2010-09-07
申请号：US12364608
申请日：2009-02-03
申请人： Yat-Tung Lam , Pantas Sutardja
发明人： Yat-Tung Lam , Pantas Sutardja
IPC分类号： G06F13/14
CPC分类号： G11B20/14 , G06F13/00 , G06F13/14 , G11B5/09 , G11C29/00
摘要： An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation being an operation in which data is being transferred from the first hardware component to the second hardware component. A second pin to receive a second clock signal sourced from the second hardware component during a second operation, the second operation being an operation in which data is being transferred from the second hardware component to the first hardware component. A third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the first operation and the second operation. The first gate control signal is gated based on the first clock signal or the second clock signal.
摘要翻译：接口支持第一硬件组件和第二硬件组件之间的信令协议。接口包括第一引脚，用于在第一操作期间向第二硬件部件提供源自第一硬件部件的第一时钟信号，第一操作是数据正在从第一硬件部件传输到第二硬件部件的操作。第二引脚，用于在第二操作期间接收来自第二硬件部件的第二时钟信号，第二操作是数据正在从第二硬件部件传送到第一硬件部件的操作。第三引脚，用于向第二硬件组件提供源自第一硬件组件的第一门控制信号，第一门控制信号在第一操作和第二操作期间同步第一硬件组件与第二硬件组件之间的数据传输。第一门控信号基于第一时钟信号或第二时钟信号选通。

7. 发明授权

US07281065B1 Long latency interface protocol 有权
标题翻译：长延时接口协议
公开(公告)号：US07281065B1
公开(公告)日：2007-10-09
申请号：US09759151
申请日：2001-01-16
申请人： Yat-Tung Lam , Pantas Sutardja
发明人： Yat-Tung Lam , Pantas Sutardja
IPC分类号： G06F13/00
CPC分类号： G11B20/14 , G06F13/00 , G06F13/14 , G11B5/09 , G11C29/00
摘要： A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial control data signal has a variable number m of words, wherein each of said m words comprises n bits, and wherein at least one of said n bits of each of said m words includes information indicating whether a subsequent word of said serial control data signal will follow. A data circuit that transmits or receives data under the control of the serial control data signal.
摘要翻译：系统包括读/写通道和硬盘控制器。硬盘控制器包括与读/写通道通信的等待时间无关的接口。串行控制数据电路发送包括串行控制数据的串行控制数据信号，其中串行控制数据信号具有可变数量的字，其中所述m个字中的每一个包括n位，并且其中，所述n位中的至少一个所述m个字中的每一个包括指示所述串行控制数据信号的后续字是否将跟随的信息。在串行控制数据信号的控制下发送或接收数据的数据电路。

8. 发明授权

US07120656B1 Movable tap finite impulse response filter 有权
标题翻译：可动抽头有限脉冲响应滤波器
公开(公告)号：US07120656B1
公开(公告)日：2006-10-10
申请号：US09761190
申请日：2001-01-18
申请人： Yat-Tung Lam , Sehat Sutardja
发明人： Yat-Tung Lam , Sehat Sutardja
IPC分类号： G06F17/10
CPC分类号： H03H17/0248 , H03H17/0009 , H03H17/06 , H04B3/23
摘要： A Finite Impulse Response (FIR) filter is provided including a coefficient generator to generate first and second coefficients, a first control conductor, and a second control conductor. A controller is coupled to a first end of the first control conductor and a first end of the second control conductor. A shared wiring is provided having its first end coupled to the coefficient generator. A first memory is coupled to a second end of the shared wiring and coupled to a second end of the first control conductor to store the first coefficient in response to the controller. A first multiplier is responsive to the first coefficient stored in the first memory and the input, and a first delay circuit is responsive to an input. A second memory is coupled to the second end of the shared wiring and coupled to a second end of the second control conductor to store the second coefficient in response to the controller, and a second multiplier is responsive to the second coefficient stored in the second memory and the first delay element.
摘要翻译：提供了一种有限脉冲响应（FIR）滤波器，包括产生第一和第二系数的系数发生器，第一控制导体和第二控制导体。控制器耦合到第一控制导体的第一端和第二控制导体的第一端。提供共享布线，其第一端耦合到系数发生器。第一存储器耦合到共享布线的第二端，并且耦合到第一控制导体的第二端，以响应于控制器存储第一系数。第一乘法器响应存储在第一存储器和输入中的第一系数，并且第一延迟电路响应输入。第二存储器耦合到共享布线的第二端并且耦合到第二控制导体的第二端以响应于控制器存储第二系数，并且第二乘法器响应于存储在第二存储器中的第二系数和第一延迟元件。

9. 发明授权

US08184391B1 Phase-adjustment of divided clock in disk head read circuit 有权
标题翻译：磁头读取电路中分频时钟的相位调整
公开(公告)号：US08184391B1
公开(公告)日：2012-05-22
申请号：US13043236
申请日：2011-03-08
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G11B5/09
CPC分类号： G11B27/3027 , G11B5/012 , G11B20/1426 , G11B2220/20 , H03L7/06
摘要： A read circuit including a bit detector, a synchronization mark detector, and a clock generator. The bit detector is configured to output serial bit data including a plurality of bits according to a first clock signal and stored digital data. The synchronization mark detector is configured to detect a synchronization marker in the serial bit data and output a synchronization pulse in response to the synchronization marker. The clock generator is configured to receive the first clock signal and divide the first clock signal to provide a divided clock output based on the synchronization pulse.
摘要翻译：包括位检测器，同步标记检测器和时钟发生器的读电路。位检测器被配置为根据第一时钟信号和存储的数字数据输出包括多个位的串行位数据。同步标记检测器被配置为检测串行位数据中的同步标记，并响应于同步标记输出同步脉冲。时钟发生器被配置为接收第一时钟信号并且划分第一时钟信号以提供基于同步脉冲的分频时钟输出。

10. 发明授权

US07903359B1 Adjustment of divided clock in disk head read circuit 有权
标题翻译：磁头阅读电路中分频时钟的调整
公开(公告)号：US07903359B1
公开(公告)日：2011-03-08
申请号：US11879487
申请日：2007-07-17
申请人： Yat-Tung Lam
发明人： Yat-Tung Lam
IPC分类号： G11B5/09
CPC分类号： G11B27/3027 , G11B5/012 , G11B20/1426 , G11B2220/20 , H03L7/06
摘要： A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.
摘要翻译：用于根据来自磁盘头的模拟数据向磁盘控制器提供多位磁盘数据的读取电路包括低频时钟发生器，其相位可响应于模拟磁盘数据中的同步标记的检测而可调节。高频时钟被锁定到磁盘头的输出端，并且使A / D转换器和位检测器的操作同步，该位检测器基于A / D输出产生经验证的单位。串行到并行转换器将位检测器的单位输出转换为并行输出，并行输出被锁存到多位磁盘数据，供磁盘控制器根据低频时钟使用。低频时钟由来自高频时钟的时钟发生器产生，具有响应于同步标记检测器可调节的相位。

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