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1. 发明授权

US08281107B2 Method of sharing coarse grained array and processor using the method 有权
标题翻译：使用该方法共享粗粒数组和处理器的方法
公开(公告)号：US08281107B2
公开(公告)日：2012-10-02
申请号：US12032709
申请日：2008-02-18
申请人： Yeon Gon Cho , Suk Jin Kim , Sang Suk Lee , Junhee Kim , Jeongwook Kim
发明人： Yeon Gon Cho , Suk Jin Kim , Sang Suk Lee , Junhee Kim , Jeongwook Kim
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/3828 , G06F9/3877 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.
摘要翻译：提供了一种共享粗粒度阵列的方法和使用该方法的处理器。处理器包括第一处理器核心，其包括执行第一指令集的多个第一功能单元，包括执行第二指令集的多个第二功能单元的第二处理器核心和包括多个第三功能块的粗粒度阵列执行第一指令集和/或第二指令集的指令的一部分的单元，而不是第一处理器核和/或第二处理器核。

2. 发明申请

US20090055626A1 METHOD OF SHARING COARSE GRAINED ARRAY AND PROCESSOR USING THE METHOD 有权
标题翻译：使用该方法共享粗粒度阵列和处理器的方法
公开(公告)号：US20090055626A1
公开(公告)日：2009-02-26
申请号：US12032709
申请日：2008-02-18
申请人： Yeon Gon CHO , Suk Jin Kim , Sang Suk Lee , Junhee Kim , Jeongwook Kim
发明人： Yeon Gon CHO , Suk Jin Kim , Sang Suk Lee , Junhee Kim , Jeongwook Kim
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3828 , G06F9/3877 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.
摘要翻译：提供了一种共享粗粒度阵列的方法和使用该方法的处理器。处理器包括第一处理器核心，其包括执行第一指令集的多个第一功能单元，包括执行第二指令集的多个第二功能单元的第二处理器核心和包括多个第三功能块的粗粒度阵列执行第一指令集和/或第二指令集的指令的一部分的单元，而不是第一处理器核和/或第二处理器核。

3. 发明授权

US08495303B2 Processor and computer system with buffer memory 有权
标题翻译：具有缓冲存储器的处理器和计算机系统
公开(公告)号：US08495303B2
公开(公告)日：2013-07-23
申请号：US12176605
申请日：2008-07-21
申请人： Sang Suk Lee , Suk Jin Kim , Yeon Gon Cho
发明人： Sang Suk Lee , Suk Jin Kim , Yeon Gon Cho
IPC分类号： G06F13/00
CPC分类号： G06F12/0846 , G06F9/3824
摘要： A processor and a computing system include a processor core and a buffer memory to read word data from a memory. The read word data includes first byte data read by the processor core from the memory. The buffer memory also stores the read word data, and determines whether second byte data requested by the processor core is stored in the buffer memory.
摘要翻译：处理器和计算系统包括处理器核心和用于从存储器读取字数据的缓冲存储器。读字数据包括处理器核从存储器读取的第一字节数据。缓冲存储器还存储读字数据，并且确定处理器核请求的第二字节数据是否被存储在缓冲存储器中。

4. 发明申请

US20090228659A1 PROCESSOR AND COMPUTING SYSTEM 有权
标题翻译：处理器和计算系统
公开(公告)号：US20090228659A1
公开(公告)日：2009-09-10
申请号：US12176605
申请日：2008-07-21
申请人： Sang Suk LEE , Suk Jin Kim , Yeon Gon Cho
发明人： Sang Suk LEE , Suk Jin Kim , Yeon Gon Cho
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F9/3824
摘要： A processor and a computing system are provided. A processor includes a processor core, and a buffer memory to read word data from a memory, the read word data including first byte data read by the processor core from the memory, and to store the read word data, wherein the buffer memory determines whether second byte data requested by the processor core is stored in the buffer memory.
摘要翻译：提供处理器和计算系统。处理器包括处理器内核和从存储器读取字数据的缓冲存储器，所述读字数据包括处理器核从存储器读取的第一字节数据，并存储读字数据，其中缓冲存储器确定是否由处理器核心请求的第二字节数据被存储在缓冲存储器中。

5. 发明授权

US08395630B2 Format conversion apparatus from band interleave format to band separate format 有权
标题翻译：格式转换装置从频带交织格式到频带分离格式
公开(公告)号：US08395630B2
公开(公告)日：2013-03-12
申请号：US11769319
申请日：2007-06-27
申请人： Jong Myon Kim , Jun Jin Kong , Jeongwook Kim , Suk Jin Kim , Soojung Ryu , Kyoung June Min , Dong-Hoon Yoo , Dong Kwan Suh , Yeon Gon Cho
发明人： Jong Myon Kim , Jun Jin Kong , Jeongwook Kim , Suk Jin Kim , Soojung Ryu , Kyoung June Min , Dong-Hoon Yoo , Dong Kwan Suh , Yeon Gon Cho
IPC分类号： G09G5/39
CPC分类号： G06T3/606
摘要： A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.
摘要翻译：提供将频带交织格式的图像数据转换成带分离格式的图像数据的格式转换装置。该装置包括：存储器，其存储频带交织格式的图像数据; 以及转换模块，其通过增加每个步幅的存储器的读取地址来读取存储器，并将频带交织格式的图像数据转换为带分离格式的图像数据。

6. 发明授权

US08443174B2 Processor and method of performing speculative load operations of the processor 有权
标题翻译：处理器和执行处理器的推测加载操作的方法
公开(公告)号：US08443174B2
公开(公告)日：2013-05-14
申请号：US11838488
申请日：2007-08-14
申请人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
发明人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3842
摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.
摘要翻译：提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用一种类似软件的方法，从而提高处理器的性能。

7. 发明申请

US20080209188A1 PROCESSOR AND METHOD OF PERFORMING SPECULATIVE LOAD OPERATIONS OF THE PROCESSOR 有权
标题翻译：处理器的执行和执行分析负载运算的方法
公开(公告)号：US20080209188A1
公开(公告)日：2008-08-28
申请号：US11838488
申请日：2007-08-14
申请人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
发明人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
IPC分类号： G06F9/38
CPC分类号： G06F9/3842
摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.
摘要翻译：提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用一种类似软件的方法，从而提高处理器的性能。

8. 发明授权

US08560795B2 Memory arrangement for multi-processor systems including a memory queue 有权
标题翻译：包括内存队列在内的多处理器系统的内存布置
公开(公告)号：US08560795B2
公开(公告)日：2013-10-15
申请号：US11966832
申请日：2007-12-28
申请人： Bingfeng Mei , Suk Jin Kim , Osman Allam
发明人： Bingfeng Mei , Suk Jin Kim , Osman Allam
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F13/1642
摘要： A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
摘要翻译：公开了适用于多处理器系统或阵列的硬件存储器架构或布置。在一个方面，存储器装置包括功能单元（例如，计算单元）和功能单元访问（用于写入和/或读取访问）的至少一个存储器件之间的至少一个存储器队列。

9. 发明申请

US20080068375A1 Method and system for early Z test in title-based three-dimensional rendering 审中-公开
标题翻译：基于标题的三维渲染的早期Z检验方法与系统
公开(公告)号：US20080068375A1
公开(公告)日：2008-03-20
申请号：US11655244
申请日：2007-01-19
申请人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
发明人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.
摘要翻译：提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

10. 发明授权

US06425273B1 Tubular lever lock 失效
标题翻译：管状杆锁
公开(公告)号：US06425273B1
公开(公告)日：2002-07-30
申请号：US09466695
申请日：1999-12-20
申请人： Dae Young Kim , Suk Jin Kim
发明人： Dae Young Kim , Suk Jin Kim
IPC分类号： B60R2502
CPC分类号： E05B55/005 , E05B13/002 , E05B13/108 , Y10T70/5416 , Y10T70/5496 , Y10T70/5832 , Y10T292/57 , Y10T292/93
摘要： A tubular lever lock includes a protruded connection part formed at the cross section of a pawl which slides along an inner spindle and interfaced with the operation of an eccentric hole of an operation globe. The spindles are structured to form and to protrude with a square pole passing through a latch by an appropriate distance. A key holder is formed on an outer bundle and is connected with a lock cylinder of an outer spindle, which enables a catch hub installed inwardly and elastically to rotate. With regard to the inner bundle and outer bundle, when built in, the key holder of the outer bundle causes connection with the operation globe through a square hole of a catch hub as well as a hole of the square pole.
摘要翻译：管状杠杆锁包括形成在棘爪的横截面上的突出连接部分，其沿着内主轴滑动并与操作球体的偏心孔的操作接合。主轴构造成形成并突出有方形的杆穿过闩锁适当的距离。钥匙保持器形成在外束上并且与外心轴的锁芯连接，这使得能够向内并弹性地旋转的止动轮毂。对于内束和外束，当内置钥匙架时，外束的钥匙架通过捕获轮毂的方孔以及方杆的孔与操作球体连接。

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