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    • 4. 发明授权
    • Memory controller and signal synchronizing method thereof
    • 存储器控制器及其信号同步方法
    • US07890786B2
    • 2011-02-15
    • US11948800
    • 2007-11-30
    • Yi Lin ChenYi Chih Huang
    • Yi Lin ChenYi Chih Huang
    • G06F1/04
    • G06F13/1689
    • A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.
    • 存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间,使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步,因此计数电路可以根据时钟精确地计数到预定时间 信号并输出​​使能信号以启用数据控制信号。 本发明还提供了一种用于存储器控制器的信号同步方法。
    • 5. 发明申请
    • MEMORY CONTROLLER AND SIGNAL SYNCHRONIZING METHOD THEREOF
    • 内存控制器及其信号同步方法
    • US20080133959A1
    • 2008-06-05
    • US11948800
    • 2007-11-30
    • Yi Lin ChenYi Chih Huang
    • Yi Lin ChenYi Chih Huang
    • G06F1/06
    • G06F13/1689
    • A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.
    • 存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间,使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步,因此计数电路可以根据时钟精确地计数到预定时间 信号并输出​​使能信号以启用数据控制信号。 本发明还提供了一种用于存储器控制器的信号同步方法。