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1. 发明授权

US09201415B2 Internal control signal regulation circuit 有权
标题翻译：内部控制信号调节电路
公开(公告)号：US09201415B2
公开(公告)日：2015-12-01
申请号：US13341682
申请日：2011-12-30
申请人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K19/00 , G05B19/042
CPC分类号： G05B19/042 , G05B2219/23314 , G05B2219/24036 , G05B2219/24037
摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.
摘要翻译：内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

2. 发明申请

US20130041612A1 INTERNAL CONTROL SIGNAL REGURATION CIRCUIT 有权
标题翻译：内部控制信号恢复电路
公开(公告)号：US20130041612A1
公开(公告)日：2013-02-14
申请号：US13341682
申请日：2011-12-30
申请人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
IPC分类号： G06F19/00
CPC分类号： G05B19/042 , G05B2219/23314 , G05B2219/24036 , G05B2219/24037
摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.
摘要翻译：内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

3. 发明授权

US08378726B2 Clock signal duty correction circuit 有权
标题翻译：时钟信号占空比校正电路
公开(公告)号：US08378726B2
公开(公告)日：2013-02-19
申请号：US12846669
申请日：2010-07-29
申请人： Yong Ju Kim , Dae Han Kwon , Won Joo Yun , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Won Joo Yun , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要翻译：时钟信号占空比校正电路包括：第一转移定时控制单元，被配置为通过使用时钟信号产生用于控制占空比校正时钟信号的上升定时的第一控制信号; 第二转移定时控制单元，被配置为通过使用根据代码信号的时钟信号来生成用于改变占空比校正时钟信号的下降定时的第二控制信号; 以及差分缓冲器单元，被配置为响应于所述第一控制信号和所述第二控制信号而生成其上升时间或下降时间被调整的占空比校正时钟信号。

4. 发明申请

US20090149142A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20090149142A1
公开(公告)日：2009-06-11
申请号：US12179486
申请日：2008-07-24
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： G06F3/033
CPC分类号： G06F13/4072
摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
摘要翻译：接收机电路能够改善其操作特性。接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

5. 发明授权

US08916975B2 Semiconductor memory device having pads 有权
标题翻译：具有衬垫的半导体存储器件
公开(公告)号：US08916975B2
公开(公告)日：2014-12-23
申请号：US12493617
申请日：2009-06-29
申请人： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Chang Kun Park , Seong Hwi Song , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： H01L23/48 , H01L23/52 , H01L23/528 , H01L23/00
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/09 , H01L27/1052 , H01L2224/061 , H01L2224/0612 , H01L2224/06515 , H01L2224/091 , H01L2224/09515 , H01L2924/14 , H01L2924/1434 , H01L2924/30101 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
摘要翻译：半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。这对数据线被布置为彼此相邻并且接收一对差分数据信号。电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

6. 发明授权

US08810274B2 On-die termination circuit 有权
标题翻译：片上终端电路
公开(公告)号：US08810274B2
公开(公告)日：2014-08-19
申请号：US13657123
申请日：2012-10-22
申请人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

7. 发明授权

US07915939B2 Duty cycle correction apparatus and semiconductor integrated circuit having the same 有权
标题翻译：占空比校正装置和具有该占空比校正装置的半导体集成电路
公开(公告)号：US07915939B2
公开(公告)日：2011-03-29
申请号：US12407727
申请日：2009-03-19
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/0814
摘要： A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.
摘要翻译：占空比校正装置包括：固定延迟单元，被配置为将固定延迟时间设置为DLL时钟信号，并产生延迟上升时钟信号; 可变延迟单元，被配置为响应于控制信号延迟所述DLL时钟信号并产生延迟下降时钟信号; 占空比校正单元，被配置为产生与延迟上升时钟信号和延迟下降时钟信号的边沿定时一致的校正上升时钟信号和校正下降时钟信号; 以及延迟控制单元，被配置为检测所述校正上升时钟信号和所述校正下降时钟信号的占空比，并产生所述控制信号。

8. 发明申请

US20100060332A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100060332A1
公开(公告)日：2010-03-11
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

9. 发明申请

US20090206901A1 DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION 失效
标题翻译：具有降低电流消耗的占空比校正电路
公开(公告)号：US20090206901A1
公开(公告)日：2009-08-20
申请号：US12333193
申请日：2008-12-11
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.
摘要翻译：一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

10. 发明授权

US08018265B1 Differential signal generation circuit 有权
标题翻译：差分信号发生电路
公开(公告)号：US08018265B1
公开(公告)日：2011-09-13
申请号：US12840255
申请日：2010-07-20
申请人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： H03K5/13
CPC分类号： H03K5/1515
摘要： A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.
摘要翻译：差分信号发生电路包括：逆变器阵列，被配置为顺序地反转输入信号以产生多个延迟信号; 以及相位混合器，被配置为以预设的混合比混合多个延迟信号中的第一延迟信号的相位和第二延迟信号的相位，以产生第一差分信号。第一延迟信号具有来自输入信号的第一延迟，并且第二延迟信号具有来自输入信号的第二延迟。差分信号生成电路被配置为从与第一和第二延迟的介质相对应的输入信号产生具有第三延迟的第三延迟信号，并且第三延迟信号被进一步延迟以产生第二差分信号。

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