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1. 发明授权

US07272055B2 Method and apparatus for timing adjustment 有权
公开(公告)号：US07272055B2
公开(公告)日：2007-09-18
申请号：US11269741
申请日：2005-11-09
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

2. 发明申请

US20060140045A1 Method and apparatus for timing adjustment 有权
公开(公告)号：US20060140045A1
公开(公告)日：2006-06-29
申请号：US11269741
申请日：2005-11-09
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C8/00 , G11C7/22 , G11C7/00 , G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

3. 发明申请

US20100315892A1 METHOD AND APPARATUS FOR TIMING ADJUSTMENT 有权
标题翻译：用于时序调整的方法和装置
公开(公告)号：US20100315892A1
公开(公告)日：2010-12-16
申请号：US12851122
申请日：2010-08-05
申请人： Yoshihiro KISHIMOTO , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro KISHIMOTO , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

4. 发明申请

US20120081973A1 METHOD AND APPARATUS FOR TIMING ADJUSTMENT 有权
标题翻译：用于时序调整的方法和装置
公开(公告)号：US20120081973A1
公开(公告)日：2012-04-05
申请号：US13311318
申请日：2011-12-05
申请人： Yoshihiro KISHIMOTO , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro KISHIMOTO , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

5. 发明授权

US08634259B2 Method and apparatus for timing adjustment 有权
标题翻译：用于定时调整的方法和装置
公开(公告)号：US08634259B2
公开(公告)日：2014-01-21
申请号：US13311318
申请日：2011-12-05
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

6. 发明授权

US08094506B2 Method and apparatus for timing adjustment 有权
标题翻译：用于定时调整的方法和装置
公开(公告)号：US08094506B2
公开(公告)日：2012-01-10
申请号：US12851122
申请日：2010-08-05
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

7. 发明授权

US07782686B2 Method and apparatus for timing adjustment 有权
标题翻译：用于定时调整的方法和装置
公开(公告)号：US07782686B2
公开(公告)日：2010-08-24
申请号：US12184797
申请日：2008-08-01
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从在选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

8. 发明授权

US07414901B2 Method and apparatus for timing adjustment 有权
标题翻译：用于定时调整的方法和装置
公开(公告)号：US07414901B2
公开(公告)日：2008-08-19
申请号：US11889822
申请日：2007-08-16
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

9. 发明申请

US20070291555A1 Method and apparatus for timing adjustment 有权
标题翻译：用于定时调整的方法和装置
公开(公告)号：US20070291555A1
公开(公告)日：2007-12-20
申请号：US11889822
申请日：2007-08-16
申请人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
发明人： Yoshihiro Kishimoto , Yuji Sekiguchi , Yoichiro Miki
IPC分类号： G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22
摘要： A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
摘要翻译：来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据值比较部分和延迟确定部分的确定。

10. 发明授权

US06911851B2 Data latch timing adjustment apparatus 失效
标题翻译：数据锁定定时调整装置
公开(公告)号：US06911851B2
公开(公告)日：2005-06-28
申请号：US10715538
申请日：2003-11-19
申请人： Yuji Sekiguchi , Yoichiro Miki
发明人： Yuji Sekiguchi , Yoichiro Miki
IPC分类号： H03L7/081 , H03L7/00 , H03L7/06
CPC分类号： H03L7/0812
摘要： In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to a delay selecting section. A selection part outputs, to a latch circuit, a delayed pulse signal obtained by delaying the latch pulse signal by the front delay circuit. The latch circuit delays the checking data piece from the memory at the reception of the delayed pulse signal. Then, the next data piece is read out from the memory and the selection part outputs, to the latch circuit, a delayed pulse signal delayed by the delay circuit at the preceding stage.
摘要翻译：在数据锁存定时调整装置中，读取控制部读出写入存储器的检查数据存储部中的第一检查数据片，并将锁存脉冲信号输出到延迟选择部。选择部分向闩锁电路输出通过由前延迟电路延迟锁存脉冲信号而获得的延迟脉冲信号。在延迟的脉冲信号的接收时，锁存电路使检查数据段从存储器延迟。然后，从存储器读出下一个数据段，并且选择部分向锁存电路输出在前一级由延迟电路延迟的延迟脉冲信号。

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