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1. 发明授权

US08421138B2 Magnetic tunneling junction device with recessed magnetic free layer 失效
标题翻译：具有嵌入式磁性自由层的磁隧道连接装置
公开(公告)号：US08421138B2
公开(公告)日：2013-04-16
申请号：US13089534
申请日：2011-04-19
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/02
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： A magnetic pinned layer is formed over a substrate. An insulating film is formed over the magnetic pinned layer. A recess is formed in and through the insulating film. A tunneling insulating film is formed over a bottom of the recess. A first magnetic free layer is formed over the bottom of the recess via the tunneling insulating film. A second magnetic free layer is formed over the insulating film and made of a same material as the first magnetic free layer. A non-magnetic film is formed on sidewalls of the recess, extending from the first magnetic free layer to the second magnetic free layer and made of oxide of the material of the first magnetic free layer. An upper electrode is disposed over the first magnetic free layer, non-magnetic film and second magnetic free layer, and electrically connected to the first magnetic free layer and second magnetic free layer.
摘要翻译：在衬底上形成磁性被钉扎层。绝缘膜形成在磁性钉扎层上。在绝缘膜上形成凹槽。隧道绝缘膜形成在凹部的底部上。通过隧道绝缘膜在凹部的底部上形成第一无磁性层。第二无磁性层形成在绝缘膜上并由与第一无磁性层相同的材料制成。在凹部的侧壁上形成非磁性膜，该第一磁性自由层从第一磁性自由层延伸到第二无磁性层，并由第一磁性层的材料的氧化物构成。上电极设置在第一磁性自由层，非磁性膜和第二无磁性层上，并电连接到第一磁性自由层和第二无磁性层。

2. 发明申请

US20110159609A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110159609A1
公开(公告)日：2011-06-30
申请号：US12971079
申请日：2010-12-17
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/02
CPC分类号： H01L27/228
摘要： A method of manufacturing a semiconductor device includes: forming first conductive layer on semiconductor substrate; forming a magnetic film on the first conductive layer; forming second conductive layer on the magnetic film; forming a first mask layer on the second conductive layer; patterning the second conductive layer; patterning the magnetic film; forming a first insulating film on the first conductive layer to cover side surfaces of the patterned second conductive layer and the patterned magnetic film; forming a second mask layer on the first insulating film to cover the patterned second conductive layer, the patterned magnetic film, and the first insulating film; patterning the first insulating film; patterning the first conductive layer; forming a second insulating film on the semiconductor substrate to cover the patterned second conductive layer, the patterned magnetic film, and the patterned first conductive layer; and forming a third insulating film on the second insulating film.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成第一导电层; 在所述第一导电层上形成磁性膜; 在所述磁性膜上形成第二导电层; 在所述第二导电层上形成第一掩模层; 图案化第二导电层; 图案化磁膜; 在所述第一导电层上形成第一绝缘膜以覆盖所述图案化的第二导电层和所述图案化的磁性膜的侧表面; 在第一绝缘膜上形成第二掩模层以覆盖图案化的第二导电层，图案化的磁性膜和第一绝缘膜; 图案化第一绝缘膜; 图案化第一导电层; 在所述半导体衬底上形成第二绝缘膜以覆盖所述图案化的第二导电层，所述图案化的磁性膜和所述图案化的第一导电层; 以及在所述第二绝缘膜上形成第三绝缘膜。

3. 发明授权

US08828742B2 Method of manufacturing magnetoresistive effect element that includes forming insulative sidewall metal oxide layer by sputtering particles of metal material from patterned metal layer 有权
标题翻译：制造磁阻效应元件的方法包括通过从图案化的金属层溅射金属材料的颗粒来形成绝缘的侧壁金属氧化物层
公开(公告)号：US08828742B2
公开(公告)日：2014-09-09
申请号：US13290779
申请日：2011-11-07
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/473 , H01L43/12 , H01L43/08 , H01L27/22
CPC分类号： H01L27/228 , H01L43/08 , H01L43/12
摘要： A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.
摘要翻译：制造磁阻效应元件的方法包括在基板的上方形成第一电极，在第一电极的上方形成金属材料的金属层，在金属层的上方形成第一磁性层，在第一磁性层的上方形成隧道绝缘膜在隧道绝缘膜上形成第二磁性层，在第二磁性层上方形成第二电极层，图案化第二电极层，图案化第二磁性层，隧道绝缘膜，第一磁性层和金属层，同时在第二磁性层，隧道绝缘膜，第一磁性层和金属层的侧壁上沉积金属膜的溅射颗粒以形成侧壁金属层，并且氧化侧壁金属层以形成绝缘侧壁金属氧化物层。

4. 发明授权

US08008197B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08008197B2
公开(公告)日：2011-08-30
申请号：US12492368
申请日：2009-06-26
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76808 , H01L21/76829
摘要： A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film, removing the second mask in a wiring trench forming region including the via hole, and etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region. Removing the first mask in the wiring trench forming region includes etching the first mask and etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole.
摘要翻译：一种半导体器件的制造方法包括：在基板上依次形成具有与第一掩模不同的蚀刻性能的阻挡膜，绝缘膜，第一掩模和第二掩模，去除绝缘膜，第一掩模，和第二掩模，以在绝缘膜中形成通孔，在包括通孔的布线沟槽形成区域中去除第二掩模，并且使用第二掩模蚀刻第一掩模作为掩模以去除布线沟槽中的第一掩模形成区域。在布线沟槽形成区域中去除第一掩模包括蚀刻第一掩模并蚀刻通孔底部的阻挡膜以部分去除通孔底部的阻挡膜。

5. 发明授权

US07189643B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07189643B2
公开(公告)日：2007-03-13
申请号：US10784821
申请日：2004-02-24
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76804 , H01L21/76811 , H01L21/76813 , Y10S438/931
摘要： An SiC film, a porous silica film as an interlayer dielectric film, another SiC film, an SiO2 film, an SiN film, and an antireflection film are formed in this order on an interlayer dielectric film and Cu film. The antireflection film is coated with an organic photosensitive ArF resist, and the resist is exposed and developed to form a resist mask in which a wiring trench pattern is formed. A trench is then formed in the porous silica film, the latter SiC film, the SiO2 film, and the SiN film. Plasma processing using a hydrogen-containing gas is performed on the side surfaces of the porous silica film, thereby forming a modified layer. The exposed portion of the former SiC film is etched away to allow the trench to reach the Cu film.
摘要翻译：依次形成SiC膜，作为层间电介质膜的多孔二氧化硅膜，另一SiC膜，SiO 2膜，SiN膜和抗反射膜，依次形成在层间绝缘膜上，Cu 电影。防反射膜用有机光敏ArF抗蚀剂涂覆，并且抗蚀剂被曝光和显影以形成其中形成布线沟槽图案的抗蚀剂掩模。然后在多孔二氧化硅膜，后者SiC膜，SiO 2膜和SiN膜中形成沟槽。在多孔二氧化硅膜的侧面进行使用含氢气体的等离子体处理，由此形成改性层。蚀刻掉前SiC膜的暴露部分以允许沟槽到达Cu膜。

6. 发明申请

US20130196451A1 MANUFACTURING METHOD OF MAGNETIC TUNNELING JUNCTION DEVICE 审中-公开
标题翻译：磁性隧道接头装置的制造方法
公开(公告)号：US20130196451A1
公开(公告)日：2013-08-01
申请号：US13826920
申请日：2013-03-14
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： A method of manufacturing a magnetic tunneling junction device, includes: forming a magnetic pinned layer over a substrate; forming an insulating film over the magnetic pinned layer; forming a recess in the insulating film, the recess reaching a bottom of the insulating film; forming a tunneling insulating film over a bottom and side walls of the recess and over the insulating film; forming a magnetic free layer over the tunneling insulating film; forming an upper electrode conductive film on the magnetic free layer; and oxidizing a portion of the magnetic free layer along the side walls of the recess.
摘要翻译：一种磁性隧道接合装置的制造方法，包括：在基板上形成磁性被钉扎层; 在磁性钉扎层上形成绝缘膜; 在所述绝缘膜中形成凹部，所述凹部到达所述绝缘膜的底部; 在所述凹部的底壁和侧壁上并在所述绝缘膜上方形成隧道绝缘膜; 在隧道绝缘膜上形成无磁性层; 在所述无磁性层上形成上电极导电膜; 以及沿着所述凹部的侧壁氧化所述无磁性层的一部分。

7. 发明申请

US20100003820A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100003820A1
公开(公告)日：2010-01-07
申请号：US12492368
申请日：2009-06-26
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/306 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76808 , H01L21/76829
摘要： A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film, removing the second mask in a wiring trench forming region including the via hole, and etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region. Removing the first mask in the wiring trench forming region includes etching the first mask and etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole.
摘要翻译：一种半导体器件的制造方法包括：在基板上依次形成具有与第一掩模不同的蚀刻性能的阻挡膜，绝缘膜，第一掩模和第二掩模，去除绝缘膜，第一掩模，和第二掩模，以在绝缘膜中形成通孔，在包括通孔的布线沟槽形成区域中去除第二掩模，并且使用第二掩模蚀刻第一掩模作为掩模以去除布线沟槽中的第一掩模形成区域。在布线沟槽形成区域中去除第一掩模包括蚀刻第一掩模并蚀刻通孔底部的阻挡膜以部分去除通孔底部的阻挡膜。

8. 发明授权

US07452795B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07452795B2
公开(公告)日：2008-11-18
申请号：US11205991
申请日：2005-08-18
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/44
CPC分类号： H01L21/76835 , H01L21/76804 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： When a via-hole 26 and an interconnection trench 32 are formed in an interconnection films 16, 18 by using as a mask a hard mask 20 covering the region except via-hole forming region, and a hard mask 22 covering the region except an interconnection trench forming region, the hard mask 20 is isotropically etched to expose the upper surface of the inter-layer insulating film 18 at a periphery of the via-hole forming region and leave the hard mask 20 in the interconnection trench forming region except the periphery, and then the hard mask 20 and the insulating films 18, 16 are anisotropically etched, whereby the via-hole 26 having increased-width portion 34 at the upper part, and the interconnection trench 32 connected to the via-hole 26 at the increased-width portions 26 are formed.
摘要翻译：当通过使用覆盖除了通孔形成区域之外的区域的硬掩模20和覆盖除互连之外的区域的硬掩模22作为掩模，在互连膜16,18中形成通孔26和互连沟槽32时沟槽形成区域，硬掩模20被各向同性地蚀刻以在通孔形成区域的周围暴露层间绝缘膜18的上表面，并且将硬掩模20留在除外围之外的互连沟槽形成区域中，然后对硬掩模20和绝缘膜18,16进行各向异性蚀刻，由此在上部具有增加宽度的部分34的通孔26和在增加的通孔26处连接到通孔26的互连沟槽32。形成宽度部26。

9. 发明授权

US07196003B2 Method for manufacturing a semiconductor device suitable for the formation of a wiring layer 有权
标题翻译：适用于形成布线层的半导体器件的制造方法
公开(公告)号：US07196003B2
公开(公告)日：2007-03-27
申请号：US10774496
申请日：2004-02-10
申请人： Yoshihisa Iba
发明人： Yoshihisa Iba
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76813 , H01L21/7684
摘要： A four-layer structured hard mask composed of a SiC film, a first SiO2 film, a SiC film, and a second SiO2 film is formed on a porous silica film as an interlayer insulating film. Then, the second SiO2 film is etched with a resist mask. Subsequently, the SiC film is etched with the second SiO2 film. Thereafter, the first SiO2 film is etched with the SiC film. Subsequently, the SiC film is etched with the SiC film. Then, by etching the porous silica film with the SiC film, a wiring trench is formed. At this time, a selection ratio between the SiC film and the porous silica film is large, so that deformation of the SiC film rarely occurs, which prevents leakage caused by the deformation.
摘要翻译：在多孔二氧化硅膜上形成由SiC膜，第一SiO 2膜，SiC膜和第二SiO 2膜构成的四层结构的硬掩模作为层间绝缘膜。然后，用抗蚀剂掩模蚀刻第二SiO 2膜。随后，用第二SiO 2膜蚀刻SiC膜。此后，用SiC膜蚀刻第一SiO 2膜。随后，用SiC膜蚀刻SiC膜。然后，通过用SiC膜蚀刻多孔二氧化硅膜，形成布线沟槽。此时，SiC膜和多孔二氧化硅膜之间的选择比例大，因此很少发生SiC膜的变形，防止变形引起的泄漏。

10. 发明授权

US06894369B2 Semiconductor device having a high-dielectric gate insulation film and fabrication process thereof 有权
标题翻译：具有高电介质栅极绝缘膜的半导体器件及其制造方法
公开(公告)号：US06894369B2
公开(公告)日：2005-05-17
申请号：US10109001
申请日：2002-03-29
申请人： Kiyoshi Irino , Yusuke Morisaki , Yoshihiro Sugita , Yoshiaki Tanida , Yoshihisa Iba
发明人： Kiyoshi Irino , Yusuke Morisaki , Yoshihiro Sugita , Yoshiaki Tanida , Yoshihisa Iba
IPC分类号： H01L29/78 , C23C16/30 , C23C16/44 , C23C16/455 , H01L21/28 , H01L21/314 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/51 , H01L23/58
CPC分类号： H01L21/28194 , C23C16/308 , C23C16/45525 , C23C16/45529 , C23C16/45531 , H01L21/02164 , H01L21/0217 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/3144 , H01L21/76224 , H01L21/823456 , H01L21/823462 , H01L21/823481 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： An ultra high-speed semiconductor device has a high-K dielectric gate insulator layer, wherein spread of impurities to a Si substrate from a gate electrode through the high-K dielectric gate insulator layer, and spread of oxygen and metallic elements from the high-K dielectric gate insulator layer to the Si substrate or the gate electrode are suppressed by arranging the high-K dielectric film sandwiched by nitrogen atomic layers on the Si substrate that is covered by an oxygen atomic layer.
摘要翻译：超高速半导体器件具有高K电介质栅极绝缘体层，其中通过高K电介质栅极绝缘体层从栅电极向Si衬底扩散杂质，并且从高电介质栅极绝缘体层扩散氧和金属元素，通过在被氧原子层覆盖的Si衬底上布置由氮原子层夹持的高K电介质膜来抑制Si衬底或栅电极的K介质栅极绝缘体层。

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