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1. 发明授权

US08151226B2 Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 有权
公开(公告)号：US08151226B2
公开(公告)日：2012-04-03
申请号：US11987811
申请日：2007-12-04
申请人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
发明人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
IPC分类号： G06F17/50
摘要： An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.

2. 发明授权

US08255844B2 Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 有权
标题翻译：协同设计配套设备，协调设计支援方式，电脑产品，印刷电路板制造方法，电路设计支援装置，电路设计支援方法，电脑产品，印刷电路板制造方法
公开(公告)号：US08255844B2
公开(公告)日：2012-08-28
申请号：US11987811
申请日：2007-12-04
申请人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
发明人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.
摘要翻译： FPGA设计CAD接口单元检索由FPGA设计的CAD设备创建的引脚分配信息。 FPGA引脚信息管理单元将引脚分配信息管理为FPGA引脚信息。临时库创建单元通过使用FPGA引脚信息来创建临时组件形状类型库，并且以能够被包装设计CAD装置读取的形式将临时组件形状类型库输出到文件。

3. 发明授权

US07831944B2 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 失效
标题翻译：电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US07831944B2
公开(公告)日：2010-11-09
申请号：US11905321
申请日：2007-09-28
申请人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
发明人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks an attribute of a pin and the like by referring to the FPGA information that is retrieved from the FPGA-designing CAD apparatus and stored in a FPGA-information storing unit by the FPGA-information managing unit.
摘要翻译：包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计的CAD设备创建的诸如引脚分配信息和属性信息的FPGA信息。当执行DRC时，如在FPGA中，DRC单元通过参考从FPGA设计的CAD设备检索并存储在FPGA信息存储单元中的FPGA信息来检查引脚的属性等。 FPGA信息管理单元。

4. 发明申请

US20090049419A1 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 失效
标题翻译：电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US20090049419A1
公开(公告)日：2009-02-19
申请号：US11905321
申请日：2007-09-28
申请人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
发明人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks an attribute of a pin and the like by referring to the FPGA information that is retrieved from the FPGA-designing CAD apparatus and stored in a FPGA-information storing unit by the FPGA-information managing unit.
摘要翻译：包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计的CAD设备创建的诸如引脚分配信息和属性信息的FPGA信息。当执行DRC时，如在FPGA中，DRC单元通过参考从FPGA设计的CAD设备检索并存储在FPGA信息存储单元中的FPGA信息来检查引脚的属性等。 FPGA信息管理单元。

5. 发明申请

US20080320433A1 Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit- board manufacturing method 有权
标题翻译：协同设计配套设备，协同设计配套方法，计算机产品，印刷电路板制造方法，电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US20080320433A1
公开(公告)日：2008-12-25
申请号：US11987811
申请日：2007-12-04
申请人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
发明人： Yoshiyuki Kato , Hisashi Aoyama , Mitsuru Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.
摘要翻译： FPGA设计CAD接口单元检索由FPGA设计的CAD设备创建的引脚分配信息。 FPGA引脚信息管理单元将引脚分配信息管理为FPGA引脚信息。临时库创建单元通过使用FPGA引脚信息来创建临时组件形状类型库，并且以能够被包装设计CAD装置读取的形式将临时组件形状类型库输出到文件。

6. 发明申请

US20080134124A1 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 有权
标题翻译：电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US20080134124A1
公开(公告)日：2008-06-05
申请号：US11905129
申请日：2007-09-27
申请人： Yoshiyuki Kato , Hisashi Aoyama
发明人： Yoshiyuki Kato , Hisashi Aoyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. When creating a symbol library, if an FPGA subjected to create the symbol library is arranged in the circuit diagram, the library creating unit manages not to change a portion dividing and a pin layout of the existing symbol library arranged in the circuit diagram as much as possible. When arranging a symbol of the FPGA that a symbol library is newly created, a circuit-diagram reflecting unit arranges the symbol without changing the existing layout.
摘要翻译：包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计CAD装置创建的诸如引脚分配信息和属性信息的FPGA信息。库创建单元通过使用FPGA信息创建符号库。当创建符号库时，如果经过创建符号库的FPGA被布置在电路图中，则库创建单元管理不将布置在电路图中的现有符号库的部分划分和引脚布局改变为可能。当重新创建符号库的FPGA的符号时，电路图反射单元排列符号而不改变现有的布局。

7. 发明授权

US07904863B2 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 有权
标题翻译：电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US07904863B2
公开(公告)日：2011-03-08
申请号：US11905129
申请日：2007-09-27
申请人： Yoshiyuki Kato , Hisashi Aoyama
发明人： Yoshiyuki Kato , Hisashi Aoyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. When creating a symbol library, if an FPGA subjected to create the symbol library is arranged in the circuit diagram, the library creating unit manages not to change a portion dividing and a pin layout of the existing symbol library arranged in the circuit diagram as much as possible. When arranging a symbol of the FPGA that a symbol library is newly created, a circuit-diagram reflecting unit arranges the symbol without changing the existing layout.
摘要翻译：包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计CAD装置创建的诸如引脚分配信息和属性信息的FPGA信息。库创建单元通过使用FPGA信息创建符号库。当创建符号库时，如果经过创建符号库的FPGA被布置在电路图中，则库创建单元管理不将布置在电路图中的现有符号库的部分划分和引脚布局改变为可能。当重新创建符号库的FPGA的符号时，电路图反射单元排列符号而不改变现有的布局。

8. 发明授权

US07913220B2 Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method 失效
标题翻译：协调设计配套设备，协同设计支持方式，电脑产品，印刷电路板制造方法
公开(公告)号：US07913220B2
公开(公告)日：2011-03-22
申请号：US11905747
申请日：2007-10-03
申请人： Yoshiyuki Kato , Hisashi Aoyama
发明人： Yoshiyuki Kato , Hisashi Aoyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.
摘要翻译： FPGA设计CAD接口单元检索由FPGA设计的CAD设备创建的引脚分配信息。 FPGA引脚信息管理单元将引脚分配信息管理为FPGA引脚信息。临时库创建单元通过使用FPGA引脚信息来创建临时组件形状类型库，并且以能够被包装设计CAD装置读取的形式将临时组件形状类型库输出到文件。

9. 发明申请

US20080263500A1 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method 有权
标题翻译：电路设计支持装置，电路设计支持方法，计算机产品和印刷电路板制造方法
公开(公告)号：US20080263500A1
公开(公告)日：2008-10-23
申请号：US11902634
申请日：2007-09-24
申请人： Yoshiyuki Kato , Hisashi Aoyama
发明人： Yoshiyuki Kato , Hisashi Aoyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5068
摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and reflect the pin swap in the symbol library, the FPGA information, a circuit diagram, and a constrained condition.
摘要翻译：包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计的CAD设备创建的诸如引脚分配信息和属性信息的FPGA信息。库创建单元通过使用FPGA信息创建符号库。引脚交换处理单元从封装设计CAD设备检索引脚交换信息，并反映符号库中的引脚交换，FPGA信息，电路图和约束条件。

10. 发明授权

US07784011B2 Reflecting pin swap of PLD performed in package design in circuit design and PLD design 有权
标题翻译：在电路设计和PLD设计中的封装设计中反映了PLD的引脚交换
公开(公告)号：US07784011B2
公开(公告)日：2010-08-24
申请号：US11905128
申请日：2007-09-27
申请人： Yoshiyuki Kato , Hisashi Aoyama
发明人： Yoshiyuki Kato , Hisashi Aoyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An FPGA-information managing unit retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and reflect the pin swap in the symbol library, the FPGA information, a circuit diagram, and a constrained condition. A change-history storing unit stores therein a change history of the FPGA information. A history output unit outputs information for notifying the pin swap to the FPGA-designing CAD apparatus 10 based on the change history stored in the change-history storing unit.
摘要翻译： FPGA信息管理单元检索由FPGA设计的CAD设备创建的诸如引脚分配信息和属性信息的FPGA信息。库创建单元通过使用FPGA信息创建符号库。引脚交换处理单元从封装设计CAD设备检索引脚交换信息，并反映符号库中的引脚交换，FPGA信息，电路图和约束条件。变更历史存储单元在其中存储FPGA信息的变更历史。历史输出单元基于存储在改变历史存储单元中的变化历史输出用于将引脚交换通知给FPGA设计CAD装置10的信息。

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