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1. 发明申请

US20060113610A1 Nonvolatile memory device and method for manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060113610A1
公开(公告)日：2006-06-01
申请号：US11228696
申请日：2005-09-16
申请人： Young-Joon Kim , Dae-Woong Kim , Min Kim
发明人： Young-Joon Kim , Dae-Woong Kim , Min Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device and a method of manufacturing the same are provided. An insulation layer having a high etching rate as compared with a pad oxide layer is formed as a buffer layer between a first STI film formed as a lower part of semiconductor substrate and a second STI film formed as an upper part of the semiconductor substrate, to obtain a pillar CD for an SAP structure. The buffer layer is etched more speedily in comparison with the pad oxide layer in a procedure of etching the pad oxide layer, thus ensuring a sufficient pillar CD without an excessive wet etch-back. Accordingly, a defect occurrence such as a grooving or seam can be prevented in realizing the SAP structure, and a tunnel oxide layer can be formed with uniform thickness.
摘要翻译：提供了一种非易失性存储器件及其制造方法。形成与衬垫氧化物层相比具有高蚀刻速率的绝缘层作为形成为半导体衬底的下部的第一STI膜和形成为半导体衬底的上部的第二STI膜之间的缓冲层形成为获得SAP结构的支柱CD。在蚀刻衬垫氧化物层的过程中，与衬垫氧化物层相比，缓冲层被更快速地蚀刻，从而确保了足够的支柱CD而没有过多的湿回蚀。因此，在实现SAP结构时，可以防止诸如切槽或接缝的缺陷发生，并且可以形成具有均匀厚度的隧道氧化物层。

2. 发明授权

US07525148B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07525148B2
公开(公告)日：2009-04-28
申请号：US11228696
申请日：2005-09-16
申请人： Young-Joon Kim , Dae-Woong Kim , Min Kim
发明人： Young-Joon Kim , Dae-Woong Kim , Min Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device and a method of manufacturing the same are provided. An insulation layer having a high etching rate as compared with a pad oxide layer is formed as a buffer layer between a first STI film formed as a lower part of semiconductor substrate and a second STI film formed as an upper part of the semiconductor substrate, to obtain a pillar CD for an SAP structure. The buffer layer is etched more speedily in comparison with the pad oxide layer in a procedure of etching the pad oxide layer, thus ensuring a sufficient pillar CD without an excessive wet etch-back. Accordingly, a defect occurrence such as a grooving or seam can be prevented in realizing the SAP structure, and a tunnel oxide layer can be formed with uniform thickness.
摘要翻译：提供了一种非易失性存储器件及其制造方法。形成与衬垫氧化物层相比具有高蚀刻速率的绝缘层作为形成为半导体衬底的下部的第一STI膜和形成为半导体衬底的上部的第二STI膜之间的缓冲层形成为获得SAP结构的支柱CD。在蚀刻衬垫氧化物层的过程中，与衬垫氧化物层相比，缓冲层被更快速地蚀刻，从而确保了足够的支柱CD而没有过多的湿回蚀。因此，在实现SAP结构时，可以防止诸如切槽或接缝的缺陷发生，并且可以形成具有均匀厚度的隧道氧化物层。

3. 发明授权

US08143103B2 Package stacking system with mold contamination prevention and method for manufacturing thereof 有权
标题翻译：具有防止霉菌污染的包装堆垛系统及其制造方法
公开(公告)号：US08143103B2
公开(公告)日：2012-03-27
申请号：US13017388
申请日：2011-01-31
申请人： Young-Joon Kim , YoRim Lee
发明人： Young-Joon Kim , YoRim Lee
IPC分类号： H01L21/50
CPC分类号： H01L25/105 , H01L23/3128 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
摘要翻译：一种制造封装堆叠系统的方法，包括：提供封装衬底; 在封装基板上安装集成电路; 在集成电路上形成降压插入器; 以及在封装基板和降压插入件上成型具有台阶型材的堆叠封装主体。

4. 发明授权

US5691930A Booth encoder in a binary multiplier 失效
标题翻译： Booth编码器在二进制乘法器中
公开(公告)号：US5691930A
公开(公告)日：1997-11-25
申请号：US514048
申请日：1995-08-11
申请人： Young-Joon Kim
发明人： Young-Joon Kim
IPC分类号： G06F7/53 , G06F7/52 , G06F7/533 , H04N7/24
CPC分类号： G06F7/5338
摘要： A partial product generator in a binary multiplier for multiplying a parallel n-bit binary multiplier and a parallel m-bit binary multiplicand comprises n/2 (n being an even integer) or (n+1)/2 (n being an odd integer) number of Booth encoders, each of which generates a partial product and includes a first inverter for inverting a first two-bit extended, i.e., m+2 bits, multiplicand (ATO), a second inverter for inverting a second two-bit extended, i.e., m+2 bits, multiplicand (BTO), a first multiplexer for selecting one of the first and the second two-bit extended, inverted m+2 bit multiplicands, a plus "1" logic for adding a binary "1" to the m+2 bit binary number (CT) selected from the first multiplexer and a second multiplexer for selecting the first extended m+2 bit multiplicand, the second extended m+2 bit multiplicand or the added m+2 bit binary number, to thereby produce the partial product, wherein the selection operation of the first and the second multiplexers is controlled by a selection code derived from the n-bit multiplier.
摘要翻译：用于将并行n位二进制乘法器和并行m位二进制乘法器相乘的二进制乘法器中的部分乘积生成器包括n / 2（n是偶数整数）或（n + 1）/ 2（n是奇数）布尔编码器数量，其中每一个产生部分积，并且包括用于反转第一两比特扩展的第一反相器，即m + 2比特，被乘数（ATO），用于反转第二两比特扩展的第二反相器，即m + 2位，被乘数（BTO），用于选择第一和第二两位扩展，反相m + 2位被乘数之一的第一多路复用器，用于将二进制“1” 到从第一多路复用器选择的m + 2位二进制数（CT）和第二多路复用器，用于选择第一扩展m + 2位被乘数，第二扩展m + 2位被乘数或加上的m + 2位二进制数，从而产生部分乘积，其中控制第一和第二多路复用器的选择操作b y是从n位乘法器导出的选择码。

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