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    • 1. 发明授权
    • System and method for processing network data of a server
    • 用于处理服务器网络数据的系统和方法
    • US08555118B2
    • 2013-10-08
    • US13280363
    • 2011-10-25
    • Yu-Gang Zhang
    • Yu-Gang Zhang
    • G06F11/00
    • H04L41/0659
    • In a system and method for processing network data of a server, the server includes a timer, a switch and a storage system. The server determines whether the storage system includes overtime information of the timer when server is powered on. If the storage system includes the overtime information, the overtime information is deleted. If an operating system is started, a predetermined initial value is written into the timer to start timing, and a first network port and a second network port are disconnected through the switch. If the server works normally, a predetermined reset command is sent to the timer to reset the timer at regular intervals. If the server does not work normally, the first network port and the second network port are connected through the switch. If the timer times out, the overtime information is written into the storage system.
    • 在用于处理服务器的网络数据的系统和方法中,服务器包括定时器,交换机和存储系统。 当服务器通电时,服务器确定存储系统是否包含定时器的超时信息。 如果存储系统包含超时信息,则删除超时信息。 如果操作系统启动,则将预定的初始值写入定时器以开始定时,并且通过交换机断开第一网络端口和第二网络端口。 如果服务器正常工作,则定时器发送一个预定的复位命令,定时器定时复位。 如果服务器不能正常工作,则通过交换机连接第一个网络端口和第二个网络端口。 如果定时器超时,则超时信息被写入存储系统。
    • 4. 发明授权
    • System and method for detecting errors occurring in computing device
    • 用于检测计算设备中出现错误的系统和方法
    • US08615685B2
    • 2013-12-24
    • US13189571
    • 2011-07-25
    • Yu-Gang Zhang
    • Yu-Gang Zhang
    • G06F11/00
    • G06F11/0751G06F11/0721
    • A system and method detects errors occurring in a computing device. The computing device includes a central processing unit (CPU) and a memory. The method sets an interruption tag for the computing device and initializes the interruption tag as zero, and detects a general purpose input output (GPIO) signal output from the CPU through a GPIO interface. The method further determines whether the GPIO signal is in a first voltage level at every time interval, and adds one to the interruption tag when the GPIO signal is switched from the first voltage level to a second voltage level. In addition, the method determines that inter errors occur in the CPU if the interruption tag is equal to one, and determines that multi-bit errors occur in the memory if the interruption tag is greater than one.
    • 系统和方法检测在计算设备中发生的错误。 计算设备包括中央处理单元(CPU)和存储器。 该方法为计算设备设置中断标签,并将中断标签初始化为零,并检测通过GPIO接口从CPU输出的通用输入输出(GPIO)信号。 该方法进一步确定GPIO信号是否处于每个时间间隔的第一电压电平,并且当GPIO信号从第一电压电平切换到第二电压电平时,将其添加到中断标签。 此外,如果中断标签等于1,则该方法确定在CPU中发生间错误,并且如果中断标签大于1,则确定存储器中发生多位错误。
    • 5. 发明授权
    • Baseboard management controller and memory error detection method of computing device utilized thereby
    • 基板管理控制器和使用的计算设备的存储器错误检测方法
    • US08661306B2
    • 2014-02-25
    • US12976967
    • 2010-12-22
    • Yu-Gang Zhang
    • Yu-Gang Zhang
    • G06F11/00
    • G06F11/006G06F11/073G06F11/0772
    • A method detects a memory error of a computing device using a baseboard management controller (BMC) of the computing device. The BMC includes a microprocessor and a storage system. The method reads data of a state register of a processor of the computing device when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor. Then the method determines whether the internal error is a multiple-bit error of a memory of the computing device according to the read data. Upon the condition that the internal error is the multiple-bit error, the method records error information of the multiple-bit error in the storage system.
    • 一种方法使用计算设备的基板管理控制器(BMC)来检测计算设备的存储器错误。 BMC包括微处理器和存储系统。 当微处理器由于处理器的内部错误接收到由处理器产生的中断信号时,该方法读取计算装置的处理器的状态寄存器的数据。 然后该方法根据读取的数据确定内部错误是否是计算设备的存储器的多位错误。 在内部错误为多位错误的情况下,该方法记录存储系统中多位错误的错误信息。
    • 6. 发明授权
    • USB testing apparatus and method
    • USB测试仪器及方法
    • US08639985B2
    • 2014-01-28
    • US13326258
    • 2011-12-14
    • Yu-Gang Zhang
    • Yu-Gang Zhang
    • G06F11/00
    • G06F11/221
    • A Universal Serial Bus (USB) testing apparatus includes a Central Processing Unit (CPU); a Southbridge; a Baseboard Management Controller (BMC), connected with the Southbridge via USB. The BMC determines if a test starts or finishes, generates a first instruction of creating a virtual control computer when determining the test starts, creates a control module and a comparing module in a memory unit which are running to become the virtual control computer, and connects the memory unit with the BMC according to the first instruction. The control module sends control data to the CPU. The comparing module obtains feedback data from the CPU and compares the control data with the obtained data to determine if the control data is consistent with the obtained data, thereby determining whether the USB is working normally.
    • 通用串行总线(USB)测试装置包括中央处理单元(CPU); 南桥 一个底板管理控制器(BMC),通过USB与南桥连接。 BMC确定测试是否开始或完成,在确定测试开始时生成创建虚拟控制计算机的第一条指令,在运行成为虚拟控制计算机的存储器单元中创建控制模块和比较模块,并连接 存储单元与BMC根据第一条指令。 控制模块向CPU发送控制数据。 比较模块从CPU获取反馈数据,并将控制数据与获得的数据进行比较,以确定控制数据是否与获得的数据一致,从而确定USB是否正常工作。