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1. 发明授权

US5504384A Multi-mode adjustable piezoelectric transformer 失效
标题翻译：多模可调压电变压器
公开(公告)号：US5504384A
公开(公告)日：1996-04-02
申请号：US343352
申请日：1994-11-21
申请人： Yu-Lin Lee , Syh-Yuh Cheng , Yun-Tien Chen , Shu-Fen Liao , Wen-Chin Yeh
发明人： Yu-Lin Lee , Syh-Yuh Cheng , Yun-Tien Chen , Shu-Fen Liao , Wen-Chin Yeh
IPC分类号： H01L41/107 , H01L41/047 , H01L41/08
CPC分类号： H01L41/107
摘要： A type of piezoelectric transformer (PT) which vibrates in length extensional mode is provided. The piezoelectric transformer (PT) has a piezoelectric substrate which has a first dimension, a second dimension and a third dimension with the first dimension being longest and the third dimension being shortest. The substrate has two polarization directions parallel to the first dimension near two terminals of the first dimension and at least two opposite polarization directions on a central portion of the substrate transversely to the first dimension. The substrate further has at least two electrodes on a portion horizontal to the first dimension. Comparing with traditional piezoelectric transformers, the new one can solve the polarization difficulties and reduce audio noise output without sacrificing the electrical properties or even have better voltage transformation characteristics.
摘要翻译：提供了一种在长度延伸模式下振动的压电变压器（PT）。压电变压器（PT）具有压电基板，其具有第一尺寸，第二尺寸和第三尺寸，第一尺寸最长，第三尺寸最短。衬底具有与第一尺寸的两个端子附近的第一尺寸平行的两个偏振方向和横向于第一尺寸的衬底的中心部分上的至少两个相反的偏振方向。基板还在与第一尺寸水平的部分上具有至少两个电极。与传统的压电变压器相比，新的可以解决极化困难，降低音频噪声输出，而不牺牲电气特性，甚至具有更好的电压转换特性。

2. 发明授权

US6020242A Effective silicide blocking 失效
标题翻译：有效的硅化物阻塞
公开(公告)号：US6020242A
公开(公告)日：2000-02-01
申请号：US926590
申请日：1997-09-04
申请人： Jiunn-Yann Tsai , Shiuh-Luen Wang , Wen-Chin Yeh
发明人： Jiunn-Yann Tsai , Shiuh-Luen Wang , Wen-Chin Yeh
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10888 , H01L27/10894
摘要： A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described. The process includes forming a gate electrode above the integrated circuit substrate, forming a first dielectric layer over the gate electrode and the substrate surface, forming a second dielectric layer above the first dielectric layer, etching anisotropically the second dielectric layer to form a second spacer portion adjacent to the first dielectric layer; masking the substrate surface of the first device to protect the first dielectric layer above the first device from being removed such that the substrate surface at the second device where the metal silicide is to be formed is exposed, etching the first dielectric layer to form a first spacer portion disposed between the gate electrode of the second device and the second spacer portion, the first spacer portion extends underneath the second spacer portion such that the first spacer portion is disposed between the second spacer portion and a portion of the substrate disposed beneath the second spacer portion, exposing the substrate surface of the first device, depositing a metal layer on the substrate surface and fusing metal ions from the metal layer with silicon ions from a plurality of device elements from the portion of the substrate surface where the metal silicide is to be formed to form metal silicide contact areas above the plurality of device elements.
摘要翻译：描述了用于防止在第一器件上形成金属硅化物并且允许在集成电路衬底的第二器件的元件上形成金属硅化物的金属硅化物封装工艺。该方法包括在集成电路衬底上形成栅电极，在栅电极和衬底表面上形成第一电介质层，在第一电介质层上形成第二电介质层，各向异性蚀刻第二电介质层以形成第二间隔部分邻近第一电介质层; 掩蔽第一器件的衬底表面以保护第一器件上方的第一电介质层被去除，使得将要形成金属硅化物的第二器件处的衬底表面暴露，蚀刻第一介电层以形成第一间隔部分设置在第二装置的栅电极和第二间隔部分之间，第一间隔部分在第二间隔部分下方延伸，使得第一间隔部分设置在第二间隔部分和布置在第二间隔部分下方的基底部分之间间隔部分，暴露第一器件的衬底表面，在衬底表面上沉积金属层，并将来自金属层的金属离子与来自多个器件元件的硅离子从金属硅化物的衬底表面的部分形成为在多个器件元件上方形成金属硅化物接触区域。

3. 发明授权

US6010952A Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation 失效
标题翻译：在使器件退化最小化的同时使暴露硅的非晶化形成金属硅化物接触的方法
公开(公告)号：US6010952A
公开(公告)日：2000-01-04
申请号：US787992
申请日：1997-01-23
申请人： Jiunn-Yann Tsai , Zhihai Wang , Wen-Chin Yeh
发明人： Jiunn-Yann Tsai , Zhihai Wang , Wen-Chin Yeh
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/78 , H01L29/10
CPC分类号： H01L29/665 , H01L21/26586 , H01L21/28176 , H01L21/28518 , H01L29/66575
摘要： An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.
摘要翻译：提供了一种改进的方法，用于通过随后非晶化硅与在非晶化步骤之后施加在硅衬底和多晶硅栅电极上的金属层的反应而将硅衬底和多晶硅栅极电极表面的非晶化部分转化为金属硅化物。该改进包括将硅衬底的暴露表面和多晶硅栅电极的表面以与硅衬底的表面平面垂直的线至少15°的角度将非晶化离子束注入，从而抑制将植入的离子通过栅电极引导到MOS结构的底层栅极氧化物和沟道。相对于垂直于硅衬底表面平面的线，非晶化离子束的植入角度优选为至少30°，但不应超过60°。

4. 发明申请

US20050068303A1 Key inputting circuit of electronic device 审中-公开
标题翻译：电子设备键输入电路
公开(公告)号：US20050068303A1
公开(公告)日：2005-03-31
申请号：US10673365
申请日：2003-09-30
申请人： Chi-Yu Ho , Wen-Chin Yeh
发明人： Chi-Yu Ho , Wen-Chin Yeh
IPC分类号： G09G5/00 , H03M11/24
CPC分类号： H03M11/24
摘要： A key inputting circuit is disclosed herein. A key inputting circuit while pressing one of keys then an input reference voltage signal will have a predetermined voltage drop caused by a specific number of series resistances and a designated voltage signal will output to a CPU to determine which key is pressed.
摘要翻译：这里公开了键输入电路。按键之间的键输入电路，然后输入参考电压信号将具有由特定数量的串联电阻引起的预定电压降，并且指定的电压信号将输出到CPU以确定按下哪个键。

5. 发明授权

US07026217B1 Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate 失效
标题翻译：在氮化衬底的湿氧化下在半导体衬底上形成反熔丝的方法
公开(公告)号：US07026217B1
公开(公告)日：2006-04-11
申请号：US10697446
申请日：2003-10-29
申请人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
发明人： Arvind Kamath , Venkatesh P. Gopinath , Wen-Chin Yeh , David Pachura
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76224 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
摘要翻译：制造反熔丝的方法包括通过离子注入装置将氮引入衬底。然后在湿氧化环境中在氮化衬底上形成氧化物介电层。控制离子注入和氧化的条件以产生具有均匀厚度的电介质和当受到高电场时的低击穿电压。

6. 发明授权

US06812158B1 Modular growth of multiple gate oxides 有权
标题翻译：多栅极氧化物的模块生长
公开(公告)号：US06812158B1
公开(公告)日：2004-11-02
申请号：US10335177
申请日：2002-12-31
申请人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
发明人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31658 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.
摘要翻译：多栅极氧化物的生长。通过用不同剂量的氧化物生长阻滞剂植入晶片的不同位置，即使在暴露于相同的氧化环境之后，整个晶片也可以生长不同厚度的氧化物。该过程是模块化的，因为一个位点的植入对其他位点的生长速率没有影响。

7. 发明授权

US06329720B1 Tungsten local interconnect for silicon integrated circuit structures, and method of making same 有权
标题翻译：用于硅集成电路结构的钨局部互连及其制造方法
公开(公告)号：US06329720B1
公开(公告)日：2001-12-11
申请号：US09212450
申请日：1998-12-16
申请人： Weidan Li , Wen-Chin Yeh , Rajat Rakkhit
发明人： Weidan Li , Wen-Chin Yeh , Rajat Rakkhit
IPC分类号： H01L2348
CPC分类号： H01L21/76895
摘要： A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element. Conductive metal is then deposited over the entire structure to fill the opening. The conductive metal thereby forms a local interconnect which bridges over the conductive element to electrically connect the respective exposed metal silicide regions adjacent the conductive element, with the silicon oxide retained over the conductive element providing insulation to electrically separate the local interconnect from the conductive element. A formula is also provided for calculating the thickness range of the silicon oxide mask layer when a silicon nitride etch stop layer is utilized.
摘要翻译：描述了用于集成电路结构的局部互连，其能够跨接在导电元件上以在局部互连级别将集成电路结构的非相邻导电部分电连接在一起。在半导体衬底中形成有源器件和集成电路结构的导电元件之后，在结构上形成氧化硅掩模，导电元件由氧化硅掩模覆盖。然后在掩模中的开口下方的暴露的硅区域中形成金属硅化物。覆盖导电元件的氧化硅掩模的部分然后被保持为绝缘。然后在该结构上形成氮化硅蚀刻停止层和可平面化介电层。然后通过导电元件上的这种氮化硅和电介质层形成开口，并且与导电元件相邻的暴露的金属硅化物区域形成开口。然后将导电金属沉积在整个结构上以填充开口。因此，导电金属形成局部互连，其桥接在导电元件上，以电连接邻近导电元件的相应暴露的金属硅化物区域，保护在导电元件上的氧化硅提供绝缘以将局部互连件与导电元件电分离。当使用氮化硅蚀刻停止层时，还提供了用于计算氧化硅掩模层的厚度范围的公式。

8. 发明授权

US6017808A Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening 失效
标题翻译：用于MOSFET栅氧化物硬化的氮注入多晶硅栅极
公开(公告)号：US6017808A
公开(公告)日：2000-01-25
申请号：US957692
申请日：1997-10-24
申请人： Shiuh-Luen Wang , Chiang-Sheng Yao , Wen-Chin Yeh
发明人： Shiuh-Luen Wang , Chiang-Sheng Yao , Wen-Chin Yeh
IPC分类号： H01L29/78 , H01L21/28 , H01L21/316 , H01L29/49 , H01L29/51 , H01L21/425 , H01L21/3205
CPC分类号： H01L21/28202 , H01L21/28044 , H01L21/28123 , H01L21/28176 , H01L29/4925 , H01L29/518
摘要： A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by nitrogen implantation and annealing. At this point nitrogen concentration peaks exist at the gate oxide interfaces with the single crystal substrate and the polysilicon gate electrode. This effectively hardens the gate oxide. A third polysilicon gate electrode exists in the bulk of the polysilicon gate electrode. In the described process the region of the polysilicon layer that contains the nitrogen concentration peak is removed. An electronically active dopant may then be implanted. Alternatively, a fresh polysilicon layer may then be deposited followed by implantation of an electronically active dopant. Thus, the method of the invention avoids retardation of electronically active dopant diffusion.
摘要翻译：描述了在栅极氧化物 - 多晶硅界面处形成低掺杂浓度区域的栅极氧化物的硬化方法。将多晶硅沉积在栅极氧化物上，然后氮注入和退火。此时，在与单晶衬底和多晶硅栅电极的栅氧化物界面存在氮浓度峰。这有效地硬化了栅极氧化物。第三多晶硅栅电极存在于多晶硅栅电极的本体中。在所述工艺中，除去含有氮浓度峰的多晶硅层的区域。然后可以注入电子活性掺杂剂。或者，然后可以沉积新鲜的多晶硅层，随后注入电子活性掺杂剂。因此，本发明的方法避免了电子活性掺杂剂扩散的延迟。

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