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1. 发明授权

US08086889B2 Semiconductor integrated circuit device for scan testing 有权
标题翻译：半导体集成电路器件进行扫描测试
公开(公告)号：US08086889B2
公开(公告)日：2011-12-27
申请号：US12256535
申请日：2008-10-23
申请人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
发明人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
IPC分类号： G06F1/04 , G01R31/28
CPC分类号： G01R31/318552
摘要： A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
摘要翻译：扫描链组结构，其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理，使得扫描链组不存在于通过对由时钟提供的一个系统的时钟树的区域，并且分配区域中的连接距离变短;测试时钟输入机构，其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构实现要输入到分配区域的时钟。此外，同时执行的扫描/扫描测试在一个区域或单个区域之间被限制，并且在所有区域中以及在所有区域之间的测试通过多次测试步骤来执行。

2. 发明申请

US20090113230A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090113230A1
公开(公告)日：2009-04-30
申请号：US12256535
申请日：2008-10-23
申请人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
发明人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
IPC分类号： G01R31/3183 , G06F11/263 , G06F1/10 , H01L21/8232
CPC分类号： G01R31/318552
摘要： A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
摘要翻译：扫描链组结构，其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理，使得扫描链组不存在于通过对由时钟提供的一个系统的时钟树的区域，并且分配区域中的连接距离变短;测试时钟输入机构，其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构实现要输入到分配区域的时钟。此外，同时执行的扫描/扫描测试在一个区域或单个区域之间被限制，并且通过多次测试步骤在所有区域和所有区域之间进行测试。

3. 发明申请

US20110204908A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110204908A1
公开(公告)日：2011-08-25
申请号：US13006325
申请日：2011-01-13
申请人： Kenichi Tada , Koki Tsutsumida , Masatoshi Kawashima , Hideki Hayashi , Tsutomu Sato , Koichi Sugimoto
发明人： Kenichi Tada , Koki Tsutsumida , Masatoshi Kawashima , Hideki Hayashi , Tsutomu Sato , Koichi Sugimoto
IPC分类号： G01R31/3187
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.
摘要翻译：半导体器件被设计为便于分析采用多相时钟的集成电路的故障的位置和原因。为此，半导体器件设置有检测在集成电路中发生操作问题的错误检测单元，时钟状态保持单元，其保持预定项中的相位信息为两维或多次，相位时钟和输出单元，当错误检测单元检测到集成电路中发生操作的问题时，输出两相或更多相位时钟的预定项中的相位的信息。

4. 发明授权

US08618823B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08618823B2
公开(公告)日：2013-12-31
申请号：US13006325
申请日：2011-01-13
申请人： Kenichi Tada , Koki Tsutsumida , Masatoshi Kawashima , Hideki Hayashi , Tsutomu Sato , Koichi Sugimoto
发明人： Kenichi Tada , Koki Tsutsumida , Masatoshi Kawashima , Hideki Hayashi , Tsutomu Sato , Koichi Sugimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.
摘要翻译：半导体器件被设计为便于分析采用多相时钟的集成电路的故障的位置和原因。为此，半导体器件设置有检测在集成电路中发生操作问题的错误检测单元，时钟状态保持单元，其保持预定项中的相位信息为两维或多次，相位时钟和输出单元，当错误检测单元检测到集成电路中发生操作的问题时，输出两相或更多相位时钟的预定项中的相位的信息。

5. 发明申请

US20110074385A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110074385A1
公开(公告)日：2011-03-31
申请号：US12849807
申请日：2010-08-03
申请人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
发明人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
IPC分类号： G01R29/00 , G01F15/06
CPC分类号： G01R31/3016 , G01R19/0084 , G01R19/0092 , G01R21/00
摘要： There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).
摘要翻译：提供了一种半导体集成电路，其中环形振荡器由可变延迟电路形成，以在可变延迟电路的测试操作时使环形振荡器振荡（S2），并且确定可变延迟电路是正常的还是在取决于环形振荡器是否满足预定的单调增加条件（S6）和预定线性条件（S7）而异常。

6. 发明申请

US20100169727A1 EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD 审中-公开
标题翻译： EDA工具，半导体器件和扫描链配置方法
公开(公告)号：US20100169727A1
公开(公告)日：2010-07-01
申请号：US12647475
申请日：2009-12-26
申请人： Daisuke ITO , Hiroki Yamanaka , Koki Tsutsumida
发明人： Daisuke ITO , Hiroki Yamanaka , Koki Tsutsumida
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318591
摘要： There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain.
摘要翻译：提供了一种用于避免当扫描链中相邻的FF具有不同的逻辑值增加的频率时出现的测试时间IR下降的技术。期望值推导模块通过计算概率传播或执行逻辑模拟得出每个FF的期望值。分组模块通过参考获得的预期值将每个受试验的FF组合成多个组。扫描链配置模块将逻辑1的进气频率彼此相反的两组对齐，在一组上执行逻辑反转，并配置一个扫描链。

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