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1. 发明授权

US5818751A Single-port SRAM with no read/write collisions 失效
标题翻译：单端口SRAM，无读/写冲突
公开(公告)号：US5818751A
公开(公告)日：1998-10-06
申请号：US925358
申请日：1997-09-08
申请人： Yung-Yuan Ho , Nang-Ping Tu , Jian-Yau Yih
发明人： Yung-Yuan Ho , Nang-Ping Tu , Jian-Yau Yih
IPC分类号： G11C11/419 , G11C11/00
CPC分类号： G11C11/419
摘要： A single-port SRAM with no read/write collisions. The present invention uses some X-axis and Y-axis control circuits to reduce the amounts of lines used in the structure of the present invention, but still maintains circuitry stability.
摘要翻译：单端口SRAM，无读/写冲突。本发明使用一些X轴和Y轴控制电路来减少在本发明的结构中使用的线的数量，但仍保持电路的稳定性。

2. 发明授权

US5729498A Reduced power consumption sram 失效
标题翻译：降低功耗sram
公开(公告)号：US5729498A
公开(公告)日：1998-03-17
申请号：US670376
申请日：1996-06-25
申请人： Jian-Yau Yih , Yung-Yuan Ho , Nang-Ping Tu , Jung-Dar Ho , Chien-Cheng Tu , Shaw-Jia Hor
发明人： Jian-Yau Yih , Yung-Yuan Ho , Nang-Ping Tu , Jung-Dar Ho , Chien-Cheng Tu , Shaw-Jia Hor
IPC分类号： G11C7/12 , G11C11/419 , G11C7/00 , G11C7/02 , G11C8/00 , G11C11/00
CPC分类号： G11C11/419 , G11C7/12
摘要： The continuing need for faster and denser SRAM memories places a constant increased demand on the power consumption of the memory devices. Much of the power consumption occurs during the pre-charge phase where it is common practice to bring up all pre-charge circuits at once and hold them active until the memory operations are complete. This invention describes a design where each pre-charge circuit connected to a group of memory cells through bit lines is activated at a separate time from the other pre-charge circuits. Thus each pre-charge circuit is active only during the time that useful work is being done with that portion of the memory. This reduces power consumption by not powering on circuits and precharging bit lines before they are actually needed.
摘要翻译：对于更快和更密集的SRAM存储器的持续需求对存储器件的功耗的需求不断增加。大部分功耗发生在预充电阶段，通常的做法是一次启动所有预充电电路并保持其活动直到存储器操作完成。本发明描述了一种设计，其中通过位线连接到一组存储器单元的每个预充电电路在与其它预充电电路分开的时间被激活。因此，每个预充电电路仅在与存储器的该部分进行有用的工作的时间有效。这在实际需要之前不通过电路供电和预充电位线来降低功耗。

3. 发明授权

US5831906A Read/write collison-free static random access memory 失效
标题翻译：读/写无碰撞静态随机存取存储器
公开(公告)号：US5831906A
公开(公告)日：1998-11-03
申请号：US827043
申请日：1997-03-25
申请人： Jian-Yau Yih , Nang-Ping Tu
发明人： Jian-Yau Yih , Nang-Ping Tu
IPC分类号： G11C11/413 , G11C7/22 , G11C8/12 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C11/419 , G11C11/418 , G11C7/22 , G11C8/12
摘要： A read/write collision-free static random access memory which can perform read/write operations simultaneously without read/write collisions. The static random access memory includes a plurality of memory cells and its features are that the memory cells are divided into several memory banks wherein each bank has independent reading and writing paths. The number of memory cells for each memory bank can be determined by a specific length of memory cells between some memory cells undergoing reading operation and other memory cells undergoing writing operation, and by the reading speed of said reading operation and the writing speed of the writing operation, whereby the reading operation and the writing operation read and write to two different memory banks of the static random access memory at the same time such that read/write collisions can be prevented.
摘要翻译：无读/写冲突的读/写无冲突静态随机存取存储器，可同时执行读/写操作。静态随机存取存储器包括多个存储单元，其特征在于，存储器单元被分成若干存储体，其中每个存储体具有独立的读取和写入路径。每个存储体的存储单元的数量可以由经历读取操作的一些存储单元和正在进行写入操作的其他存储单元之间的存储单元的特定长度以及所述读取操作的读取速度和写入的写入速度来确定从而读取操作和写入操作同时读取和写入静态随机存取存储器的两个不同的存储体，从而可以防止读/写冲突。

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