专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08185570B2 Three-term input floating-point adder-subtractor 失效
标题翻译：三项输入浮点加减法器
公开(公告)号：US08185570B2
公开(公告)日：2012-05-22
申请号：US11955571
申请日：2007-12-13
申请人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
发明人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
IPC分类号： G06F7/42 , G06F7/50 , G06F11/00
CPC分类号： G06F7/485 , G06F7/49963
摘要： The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
摘要翻译：加法器 - 减法器包括预处理电路，其将三个输入的项分成具有最大值的指数的尾数，具有中间值指数的尾数和具有最小幅度指数的尾数，并输出通过右移所获得的尾数具有中值的指数的尾数和具有2n + 3位的最小指数的尾数，并且调整数字和具有最大指数的尾数，这将尾数从三个字节减少到两个项，这在两个字符的尾数上执行加法使得使最高有效位变为1的左移的归一化电路，使用来自最高有效位的第（n + 3）位作为新的粘性位的舍入电路与较低位进行逻辑或，执行舍入和指数运算单元，其输出最终指数。

2. 发明申请

US20080215660A1 Three-Term Input Floating-Point Adder-Subtractor 失效
标题翻译：三期输入浮点加法器 - 减法器
公开(公告)号：US20080215660A1
公开(公告)日：2008-09-04
申请号：US11955571
申请日：2007-12-13
申请人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
发明人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
IPC分类号： G06F7/485 , G06F7/483 , G06F17/00
CPC分类号： G06F7/485 , G06F7/49963
摘要： The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent with a width of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, a carry save adder (CSA) which reduces the mantissas from the pre-processing circuit from three terms to two terms, a carry look-ahead adder (CLA) which carries out addition on the mantissas of the two terms, a normalization circuit which makes a left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
摘要翻译：三项输入浮点加减法器包括预处理电路，其将三个输入的项分成具有最大值的指数的尾数，具有中间值的指数的尾数和具有最小值的指数的尾数，并输出通过右移具有中间值指数的尾数和具有2n + 3比特宽度的最小指数的尾数和具有最大指数的尾数的尾数获得的尾数，进位保存加法器（CSA）减少从三个术语到两个术语的预处理电路的尾数，在两个项的尾数上执行加法的进位前视加法器（CLA），进行左移以使最高有效位变为如图1所示，使用来自最高有效位的第（n + 3）位作为新的粘性位的舍入电路与较低位进行逻辑或运算，并执行舍入和指数运算比例单位输出最终指数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式