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1. 发明授权

US08223548B2 Memory device with reduced programming voltage method of reduction of programming voltage and method of reading such memory device 有权
标题翻译：具有减少编程电压的编程电压降低的存储器件和读取这种存储器件的方法
公开(公告)号：US08223548B2
公开(公告)日：2012-07-17
申请号：US12601788
申请日：2008-05-23
申请人： Yutaka Hayashi , Kazuhiko Matsumoto , Takafumi Kamimura
发明人： Yutaka Hayashi , Kazuhiko Matsumoto , Takafumi Kamimura
IPC分类号： G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0657 , H01L29/1606 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/6684 , H01L29/7781 , H01L29/792
摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.
摘要翻译：存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度，实现低编程电压。横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值温度。

2. 发明申请

US20100208522A1 MEMORY DEVICE AND READING METHOD THEREOF 有权
标题翻译：存储器件及其读取方法
公开(公告)号：US20100208522A1
公开(公告)日：2010-08-19
申请号：US12601788
申请日：2008-05-23
申请人： Yutaka Hayashi , Kazuhika Matsumoto , Takafumi Kamimura
发明人： Yutaka Hayashi , Kazuhika Matsumoto , Takafumi Kamimura
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0657 , H01L29/1606 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/6684 , H01L29/7781 , H01L29/792
摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.
摘要翻译：存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度，实现低编程电压。横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值温度。

3. 发明授权

US4811070A Heterojunction bipolar transistor with inversion layer base 失效
标题翻译：异质结双极晶体管与反型层基极
公开(公告)号：US4811070A
公开(公告)日：1989-03-07
申请号：US30747
申请日：1987-03-27
申请人： Yutaka Hayashi , Kazuhiko Matsumoto , Nobuo Hashizume
发明人： Yutaka Hayashi , Kazuhiko Matsumoto , Nobuo Hashizume
IPC分类号： H01L29/73 , H01L21/331 , H01L29/20 , H01L29/205 , H01L29/737 , H01L29/72
CPC分类号： H01L29/7373
摘要： A semiconductor device comprises a first semiconductor region having formed thereon a second semiconductor region which forms at its one surface an energy barrier with respect to minority carriers of the first semiconductor region, a conductive region in contact with the other surface of the second semiconductor region, and an induced layer formed in the operating state in a surface portion of the first semiconductor region in contact with the second semiconductor region under the conductive region, the carriers being transported across the induced layer to the first semiconductor region, whereby the conductive region acts as an emitter, the induced layer acts as a base and the first semiconductor layer acts as a collector of a transistor.
摘要翻译：半导体器件包括在其上形成有第二半导体区域的第一半导体区域，该第二半导体区域在其一个表面上形成相对于第一半导体区域的少数载流子的能量势垒，与第二半导体区域的另一表面接触的导电区域，以及在所述第一半导体区域的与所述导电区域下方的所述第二半导体区域接触的所述第一半导体区域的表面部分中形成的感应层，所述载流子跨过所述感应层传输到所述第一半导体区域，由此所述导电区域作为发射极，感应层用作基极，第一半导体层用作晶体管的集电极。

4. 发明申请

US20130224557A1 SEPARATOR FOR NON-AQUEOUS BATTERIES AND NON-AQUEOUS BATTERY EQUIPPED WITH SAME, AND PROCESS FOR MANUFACTURING SEPARATOR FOR NON-AQUEOUS BATTERIES 有权
标题翻译：非水性电池分离器和配备非水电池的非电池电池以及非水电池制造分离器的工艺
公开(公告)号：US20130224557A1
公开(公告)日：2013-08-29
申请号：US13881747
申请日：2011-10-13
申请人： Tomohiro Hayakawa , Takayoshi Hosoya , Hiroyuki Kawai , Hideo Hayashi , Yutaka Hayashi , Kohsuke Togashi , Naotaka Gotoh
发明人： Tomohiro Hayakawa , Takayoshi Hosoya , Hiroyuki Kawai , Hideo Hayashi , Yutaka Hayashi , Kohsuke Togashi , Naotaka Gotoh
IPC分类号： H01M2/16
CPC分类号： H01M2/1653 , C08G18/04 , C08G18/4009 , H01M2/162 , H01M2/1666 , H01M2/1686 , H01M10/052 , Y02E60/122 , Y02P70/54
摘要： Provided is a separator for non-aqueous batteries, capable of being usefully used in non-aqueous batteries, and a non-aqueous battery equipped with this separator. The separator for non-aqueous batteries includes: a base layer comprising a fiber aggregate, and an electrolyte-swellable resin layer formed on at least one surface of the base layer, the resin layer comprising a urethane resin (C) obtained by reacting a polyol (A) including a vinyl polymer (a1) and a polyether polyol (a2) with a polyisocyanate (B). The vinyl polymer (a1) has as a main chain a vinyl polymer (a1′) having two hydroxyl groups at one of the termini of the main chain, and a polyoxyethylene chain having a number average molecular weight of 200 to 800 as a side chain, the percentage of the polyoxyethylene chain based on the vinyl polymer (a1) being within the range of 70 mass % to 98 mass %.
摘要翻译：本发明提供一种能够用于非水电池的非水电池用隔膜，以及配备有该隔膜的非水电池。非水电池用隔膜包括：包含纤维聚集体的基层和形成在基层的至少一个表面上的电解质溶胀性树脂层，所述树脂层包含聚氨酯树脂（C），其通过使多元醇（A）包括乙烯基聚合物（a1）和聚醚多元醇（a2）与多异氰酸酯（B）。乙烯基聚合物（a1）作为主链具有在主链的一个末端具有两个羟基的乙烯基聚合物（a1'）和作为侧链的数均分子量为200〜800的聚氧乙烯链基于乙烯基聚合物（a1）的聚氧乙烯链的百分比在70质量％至98质量％的范围内。

5. 发明授权

US08450799B2 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
公开(公告)号：US08450799B2
公开(公告)日：2013-05-28
申请号：US11975923
申请日：2007-10-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/34
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

6. 发明授权

US08094484B2 Memory cell array 有权
标题翻译：存储单元阵列
公开(公告)号：US08094484B2
公开(公告)日：2012-01-10
申请号：US12644851
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和门极阈值电压以下。

7. 发明申请

US20100165696A1 Memory Cell Array 有权
标题翻译：存储单元阵列
公开(公告)号：US20100165696A1
公开(公告)日：2010-07-01
申请号：US12644608
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线或更少。

8. 发明授权

US07545018B2 High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
标题翻译：高电压工作场效应晶体管，其偏置电路及其高电压电路
公开(公告)号：US07545018B2
公开(公告)日：2009-06-09
申请号：US11063388
申请日：2005-02-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Yoshifumi Yoshida , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Yoshifumi Yoshida , Jun Osanai
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L27/092 , H01L27/1203 , H01L29/7831 , H01L29/7838 , H01L29/78645 , H01L29/78654
摘要： A high voltage operating field effect transistor has a substrate, a source region and a drain region which are spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region. At least one of a signal electric potential and a signal current is supplied to the source region, and a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential is supplied to the gate region. One end of a rectifying device is connected to the gate region, and a second constant electric potential is supplied to the other end of the rectifying device.
摘要翻译：高电压工作场效应晶体管具有在基板的表面上彼此间隔开的基板，源极区域和漏极区域，设置在基板的表面中的源极区域与源极区域之间的半导体沟道形成区域，漏极区域，设置在沟道形成区域上方的栅极区域和设置在沟道形成区域和栅极区域之间的栅极绝缘膜区域。将信号电位和信号电流中的至少一个提供给源极区域，并且具有绝对值等于或大于根据漏极电流的增减的第一恒定电位变化的偏置电位电位被提供给栅极区域。整流装置的一端与栅极区域连接，第二恒定电位被提供给整流装置的另一端。

9. 发明申请

US20090014765A1 High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
标题翻译：高电压工作场效应晶体管，其偏置电路及其高电压电路
公开(公告)号：US20090014765A1
公开(公告)日：2009-01-15
申请号：US12283639
申请日：2008-09-12
申请人： Yutaka Hayashi , Hisashi Hasegawa , Yoshifumi Yoshida , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Yoshifumi Yoshida , Jun Osanai
IPC分类号： H03K5/08 , H01L27/06
CPC分类号： H01L27/0629 , H01L27/092 , H01L27/1203 , H01L29/7831 , H01L29/7838 , H01L29/78645 , H01L29/78654
摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.
摘要翻译：高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。源区域可操作以接收信号电位和信号电流中的至少一个。半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。

10. 发明授权

US07282763B2 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
标题翻译：形成在绝缘基板上的场效应晶体管及其集成电路
公开(公告)号：US07282763B2
公开(公告)日：2007-10-16
申请号：US10228847
申请日：2002-08-27
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/94
CPC分类号： H01L29/78615 , H01L29/42384 , H01L29/78645
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation and without application of a fixed bias potential to the third region.
摘要翻译：场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和形成在半导体薄膜上的栅极绝缘膜。在栅极绝缘膜上形成第一栅电极。在第一栅电极的长度方向的相对侧的半导体薄膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。导电薄膜与第二区域和第三区域连接。第二栅电极沿着第二区形成在栅极绝缘膜上。具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。根据电路操作将第一和第四区域中的一个用作输出区域，并且不向第三区域施加固定的偏置电位。

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