专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09385183B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09385183B2
公开(公告)日：2016-07-05
申请号：US14434388
申请日：2012-12-06
申请人： Ze Chen , Tsuyoshi Kawakami , Katsumi Nakamura
发明人： Ze Chen , Tsuyoshi Kawakami , Katsumi Nakamura
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/06 , H01L29/739 , H01L29/423
CPC分类号： H01L29/0619 , H01L29/0638 , H01L29/4236 , H01L29/7395 , H01L29/7397
摘要： The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.
摘要翻译：终端区域包括环形区域（LNFLR）。多个环形P型环层规则地布置在环形区域（LNFLR）中。环区域（LNFLR）被分成多个单元，分别包括多个P型环层。每个单位的宽度是恒定的。环状区域（LNFLR）中的P型杂质的总数为N，目标耐受电压为BV [V]，每个单位的宽度为SandL [μm]，多个单位的数量为num，满足以下关系。 N≥（M×BV）γ，M = 104〜105，γ= 0.55〜1.95，SandL×num×Ecri≥2×α×BV，Ecri = 2.0〜3.0×105 [V / cm]，α= 多个单元的P型环层的宽度朝着端接区域的外侧线性地减小。

2. 发明申请

US20150279931A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150279931A1
公开(公告)日：2015-10-01
申请号：US14434388
申请日：2012-12-06
申请人： Ze CHEN , Tsuyoshi KAWAKAMI , Katsumi NAKAMURA
发明人： Ze Chen , Tsuyoshi Kawakami , Katsumi Nakamura
IPC分类号： H01L29/06
CPC分类号： H01L29/0619 , H01L29/0638 , H01L29/4236 , H01L29/7395 , H01L29/7397
摘要： The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers (12a˜120 are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers (12a˜120 respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers (12a˜12f) of the plurality of units linearly decrease toward an outside of the termination region.
摘要翻译：终端区域包括环形区域（LNFLR）。多个环状P型环状层（12a〜120）规则地排列在环状区域（LNFLR）中，环状区域（LNFLR）被分割成多个包含多个P型环状层的单元 12a〜120，单位宽度恒定，环区（LNFLR）中P型杂质总数为N，目标耐受电压为BV [V]，各单位的宽度为SandL [μm ]，并且多个单元的数量为num，满足以下关系：N≥（M×BV）γ，M = 104〜105，γ= 0.55〜1.95，SandL×num×Ecri≥2×α×BV ，Ecri = 2.0〜3.0×105 [V / cm]，α= 100〜101.多个单元的P型环层（12a〜12f）的宽度向端子区域的外侧线性地减小。

3. 发明授权

US09287391B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09287391B2
公开(公告)日：2016-03-15
申请号：US14370048
申请日：2012-03-05
申请人： Ze Chen , Katsumi Nakamura
发明人： Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/06 , H01L29/739 , H01L29/423 , H01L29/40
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/1095 , H01L29/404 , H01L29/4236 , H01L29/7397
摘要： A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.
摘要翻译：半导体器件包括其中限定有源区和边缘终端区的半导体衬底，形成在有源区中的半导体元件，以及形成在从有源区的边缘部分到边缘端接区域。第一至第四P层分别具有按此顺序降低的表面浓度P（1）至P（4），以该顺序增加的底端距离D（1）至D（4），距离B（1）到B（4）到依次增加的半导体衬底的边缘。表面浓度P（4）是半导体衬底的杂质浓度的10〜1000倍，底端距离D（4）在15〜30μm的范围内。

4. 发明授权

US09041051B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09041051B2
公开(公告)日：2015-05-26
申请号：US14111168
申请日：2011-07-05
申请人： Ze Chen , Katsumi Nakamura
发明人： Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/36 , H01L29/739 , H01L29/861 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/063 , H01L29/0696 , H01L29/0821 , H01L29/0834 , H01L29/1095 , H01L29/41708 , H01L29/7393 , H01L29/861
摘要： An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).
摘要翻译：具有栅极（7）和发射极（9）的绝缘栅双极晶体管设置在晶体管区域中。端子区域布置在晶体管区域周围。第一N型缓冲层（18）设置在晶体管区域中的N型漂移层（1）的下方。在第一N型缓冲层（18）的下方设置有P型集电体层（19）。第二N型缓冲层（20）设置在终端区域中的N型漂移层（1）的下方。集电极（21）直接连接到P型集电极层（19）和第二N型缓冲层（20）。随着与集电极（21）的距离减小，第二N型缓冲层（20）的杂质浓度降低。第二N型缓冲层（20）不与集电极（21）形成任何欧姆接触。

5. 发明申请

US20150014741A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150014741A1
公开(公告)日：2015-01-15
申请号：US14370048
申请日：2012-03-05
申请人： Ze Chen , Katsumi Nakamura
发明人： Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/739 , H01L29/06 , H01L29/423
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/1095 , H01L29/404 , H01L29/4236 , H01L29/7397
摘要： A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.
摘要翻译：半导体器件包括其中限定有源区和边缘终端区的半导体衬底，形成在有源区中的半导体元件，以及形成在从有源区的边缘部分到边缘端接区域。第一至第四P层分别具有按此顺序降低的表面浓度P（1）至P（4），以该顺序增加的底端距离D（1）至D（4），距离B（1）到B（4）到依次增加的半导体衬底的边缘。表面浓度P（4）是半导体衬底的杂质浓度的10〜1000倍，底端距离D（4）在15〜30μm的范围内。

6. 发明申请

US20140197451A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140197451A1
公开(公告)日：2014-07-17
申请号：US14111168
申请日：2011-07-05
申请人： Ze Chen , Katsumi Nakamura
发明人： Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/063 , H01L29/0696 , H01L29/0821 , H01L29/0834 , H01L29/1095 , H01L29/41708 , H01L29/7393 , H01L29/861
摘要： An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).
摘要翻译：具有栅极（7）和发射极（9）的绝缘栅双极晶体管设置在晶体管区域中。端子区域布置在晶体管区域周围。第一N型缓冲层（18）设置在晶体管区域中的N型漂移层（1）的下方。在第一N型缓冲层（18）的下方设置有P型集电体层（19）。第二N型缓冲层（20）设置在终端区域中的N型漂移层（1）的下方。集电极（21）直接连接到P型集电极层（19）和第二N型缓冲层（20）。随着与集电极（21）的距离减小，第二N型缓冲层（20）的杂质浓度降低。第二N型缓冲层（20）不与集电极（21）形成任何欧姆接触。

7. 发明申请

US20120273836A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120273836A1
公开(公告)日：2012-11-01
申请号：US13324306
申请日：2011-12-13
申请人： Koji Sadamatsu , Ze Chen , Katsumi Nakamura
发明人： Koji Sadamatsu , Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0619
摘要： A semiconductor device includes: a transistor region including an IGBT having a gate electrode and an emitter electrode; a termination region placed around the transistor region; and an extraction region placed between the transistor and the termination region and extracting redundant carriers. A P-type layer is placed on an N-type drift layer in the extraction region. The P-type layer is connected to the emitter electrode. A dummy gate electrode is placed via an insulation film on the P-type layer. The dummy gate electrode is connected to the gate electrode. Life time of carriers in the termination region is shorter than life time of carriers in the transistor region and the extraction region.
摘要翻译：半导体器件包括：晶体管区域，其包括具有栅极电极和发射极电极的IGBT; 放置在晶体管区域周围的端接区域; 以及放置在晶体管和端接区域之间并提取冗余载流子的提取区域。 P型层被放置在提取区域中的N型漂移层上。 P型层连接到发射极。通过P型层上的绝缘膜放置虚拟栅电极。虚拟栅电极连接到栅电极。终端区域中载流子的寿命短于晶体管区域和提取区域中载流子的寿命。

8. 发明授权

US08598622B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08598622B2
公开(公告)日：2013-12-03
申请号：US13324306
申请日：2011-12-13
申请人： Koji Sadamatsu , Ze Chen , Katsumi Nakamura
发明人： Koji Sadamatsu , Ze Chen , Katsumi Nakamura
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/7397 , H01L29/0619
摘要： A semiconductor device includes: a transistor region including an IGBT having a gate electrode and an emitter electrode; a termination region placed around the transistor region; and an extraction region placed between the transistor and the termination region and extracting redundant carriers. A P-type layer is placed on an N-type drift layer in the extraction region. The P-type layer is connected to the emitter electrode. A dummy gate electrode is placed via an insulation film on the P-type layer. The dummy gate electrode is connected to the gate electrode. Life time of carriers in the termination region is shorter than life time of carriers in the transistor region and the extraction region.
摘要翻译：半导体器件包括：晶体管区域，其包括具有栅极电极和发射极电极的IGBT; 放置在晶体管区域周围的端接区域; 以及放置在晶体管和端接区域之间并提取冗余载流子的提取区域。 P型层被放置在提取区域中的N型漂移层上。 P型层连接到发射极。通过P型层上的绝缘膜放置虚设栅电极。虚拟栅电极连接到栅电极。终端区域中载流子的寿命短于晶体管区域和提取区域中载流子的寿命。

9. 发明授权

US08698195B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08698195B2
公开(公告)日：2014-04-15
申请号：US13329727
申请日：2011-12-19
申请人： Daisuke Oya , Katsumi Nakamura
发明人： Daisuke Oya , Katsumi Nakamura
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/4236
摘要： A stabilizing plate portion is formed in a region of a first main surface lying between first and second insulated gate field effect transistor portions. The stabilizing plate portion includes a first stabilizing plate arranged closest to the first insulated gate field effect transistor portion and a second stabilizing plate arranged closest to the second insulated gate field effect transistor portion. An emitter electrode is electrically connected to an emitter region of each of the first and second insulated gate field effect transistor portions, electrically connected to each of the first and second stabilizing plates, and arranged on the entire first main surface lying between the first and second stabilizing plates, with an insulating layer being interposed.
摘要翻译：在位于第一和第二绝缘栅场效应晶体管部分之间的第一主表面的区域中形成稳定板部分。稳定板部分包括最靠近第一绝缘栅场效应晶体管部分布置的第一稳定板和最靠近第二绝缘栅场效应晶体管部分布置的第二稳定板。发射电极电连接到第一和第二绝缘栅场效应晶体管部分的每个的发射极区域，电连接到第一和第二稳定板中的每一个，并且布置在位于第一和第二绝缘栅极效应晶体管的第一和第二绝缘栅极稳定板，绝缘层被插入。

10. 发明授权

US07910987B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07910987B2
公开(公告)日：2011-03-22
申请号：US11267514
申请日：2005-11-07
申请人： Katsumi Nakamura
发明人： Katsumi Nakamura
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/3221 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A gate electrode is provided to fill up a trench while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode located upward beyond a P-type base layer and an N+-type emitter diffusion layer , WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film and the P-type base layer and an end surface of the gate electrode located upward beyond the trench in a section of the trench , relation of either WG≧1.3·WT or WC≧0.2 μm holds between these dimensions.
摘要翻译：提供栅极电极13，以填充沟槽300，同时覆盖其开口。假设WG表示位于P型基极层4和N +型发射极扩散层51之上的栅极电极<13>的头部的直径（截面宽度），WT表示直径（沟槽<300>的直线延伸部分的内壁和WC表示栅极氧化膜<11>与P型基极层之间的距离（沟槽300的内壁）之间的距离在沟槽<300>的部分中位于上方超过沟槽<300>的栅极电极<13>的端面，在这些尺寸之间保持WG≥3.3·WT或WC≥0.2μm的关系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式