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1. 发明授权

US10084476B1 Adaptive lossless compression in analog mixed signal environments 有权
公开(公告)号：US10084476B1
公开(公告)日：2018-09-25
申请号：US15847604
申请日：2017-12-19
申请人： Cadence Design Systems, Inc.
发明人： Jianzhou Zhao , Daniel de Fonseca Munford Argollo , Vuk Borich , Hongzhou Liu
IPC分类号： H03M7/30
CPC分类号： H03M7/30 , H03M7/3084
摘要： A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.

2. 发明授权

US09075932B1 Methods and systems for routing an electronic design using spacetiles 有权
标题翻译：使用空间布线电子设计的方法和系统
公开(公告)号：US09075932B1
公开(公告)日：2015-07-07
申请号：US13602069
申请日：2012-08-31
申请人： Jeffrey S. Salowe
发明人： Jeffrey S. Salowe
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5036 , G06F17/5077
摘要： Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punches for the muting layer, identify an area probe from the spacetiles, and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punches to form spacetiles for the routing layers, determine a via spacetile layer, identify spacetiles as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two muting layers. One of the two routing layers may be a tracked muting layer, and the other may be a trackless routing layer. The tracked muting may be gridded or gridless.
摘要翻译：各种实施例识别电子设计的布线层，通过对静电层进行空间冲压来创建空间，从空间识别区域探针，并且通过使用用于执行区域搜索的一个或多个区域探针来路由电子设计用于路由解决方案。一些实施例识别电子设计的两个路由层，执行空间冲孔以形成用于路由层的空间，确定经由空间层，基于经由空间层将空间识别为一个或多个区域探针，并且通过使用所述一个或多个区域探针用于在两个屏蔽层之间转换时执行路由解决方案的区域搜索。两个路由层中的一个可以是跟踪的静默层，另一个可以是无轨道路由层。跟踪的静音可能是网格或无格。

3. 发明授权

US08074187B2 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout 有权
标题翻译：用于将金属填充物插入集成电路（“IC”）布局的方法和装置
公开(公告)号：US08074187B2
公开(公告)日：2011-12-06
申请号：US12731057
申请日：2010-03-24
申请人： Judd Matthew Ylinen , Kwok Ming Yue
发明人： Judd Matthew Ylinen , Kwok Ming Yue
IPC分类号： G06F17/50
CPC分类号： H01L23/522 , G06F2217/12 , H01L21/76819 , H01L21/7684 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo.
摘要翻译：本发明的一些实施例提供了一种在集成电路（“IC”）布局中插入多个填充物的方法。该方法识别在IC布局的区域中的一组潜在填充，其中该潜在填充的集合具有第一填充尺寸，其中第一填充尺寸来自一组填充尺寸。该方法在潜在填充集合中的每个潜在填充周围指定光晕。对于每个潜在的填充，该方法确定指定的光晕是否与布局区域中的异物重叠。对于每个可能的填充，如果指定的光环不与IC布局区域中的异物重叠，则该方法指定IC布局区域中的合法填充。该方法在IC布局的区域插入至少一个合法填充。在一些实施方案中，卤素是间隔卤素。

4. 发明授权

US07739644B1 Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization 失效
标题翻译：方法，系统和计算机程序产品，用于放置，布局规划和合法化中的格式变形技术
公开(公告)号：US07739644B1
公开(公告)日：2010-06-15
申请号：US11838193
申请日：2007-08-13
申请人： Philip Chong , Christian Szegedy
发明人： Philip Chong , Christian Szegedy
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Disclosed are methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that the final locations of the objects are minimally perturbed from their initial starting locations and the density of objects meets certain constraints. The minimization of perturbation, or stability, of the approaches disclosed, is the key feature which is the principal benefit of the techniques disclosed. The methods described herein may be used as part of a tool for placement or floorplanning of logic gates or larger macroblocks for the design of an integrated circuit.
摘要翻译：公开了用于执行网格变形技术的方法，系统和计算机程序产品，用于计算区域上的对象的扩展，使得对象的最终位置分布在该区域上，并且使得对象的最终位置被最小程度地从它们的起始位置和物体的密度满足某些限制。所公开的方法的扰动或稳定性的最小化是所公开技术的主要益处的关键特征。本文描述的方法可以用作用于设计集成电路的逻辑门或更大宏块的放置或布局规划的工具的一部分。

5. 发明授权

US08719761B2 Method and apparatus for optimizing memory-built-in-self test 有权
标题翻译：用于优化内存自身测试的方法和装置
公开(公告)号：US08719761B2
公开(公告)日：2014-05-06
申请号：US13625682
申请日：2012-09-24
申请人： Norman Card , Puneet Arora , Steven Gregor , Navneet Kaushik
发明人： Norman Card , Puneet Arora , Steven Gregor , Navneet Kaushik
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.
摘要翻译：使用优化的存储器内置自检（MBIST）方法来测试存储器，包括生成用于存储器的紧凑模型。成本函数由影响MBIST的估计参数构成，用户可以为参数分配相对权重。估计参数包括MBIST区域，布线拥塞和定时开销，以及功耗和时序。使用优化技术最小化成本函数，从而对存储器件进行优化分组，并为MBIST测试提供优化的计划。估计的参数可以从由从各种存储器件实验导出的数据构建的紧凑模型中导出。这种方法允许电路设计者在运行完整的设计流程之前生成和修改分组和计划，从而节省时间和成本，同时仍然实现高质量的结果。

6. 发明授权

US07212217B1 Methods and apparatus for generating pixel data for multi-layer source images 有权
标题翻译：用于生成多层源图像的像素数据的方法和装置
公开(公告)号：US07212217B1
公开(公告)日：2007-05-01
申请号：US10170946
申请日：2002-06-12
申请人： Heath Feather , Richard Holmes
发明人： Heath Feather , Richard Holmes
IPC分类号： G09G5/00 , G09G5/30
CPC分类号： G06T17/005
摘要： A graphics system readily activates and deactivates layers of a multi-layer source image. Image data, such as a multi-layered integrated circuit (“IC”) design, is generated for a multi-layer source image. A pyramid of image tiles defines “on” and “off” states for elements that represent the source image. A bit plane identifies values for the elements for each layer of the source image. Mask image data is generated to zero image data associated with at least one layer of the bit plane. The graphics system generates pixel data from the mask image data, and renders the pixel data on an output display.
摘要翻译：图形系统容易地激活和去激活多层源图像的层。为多层源图像生成诸如多层集成电路（“IC”）设计的图像数据。图像块的金字塔定义了代表源图像的元素的“开”和“关”状态。位平面识别源图像的每个层的元素的值。生成掩模图像数据以使与位平面的至少一层相关联的图像数据为零。图形系统从掩模图像数据生成像素数据，并将像素数据呈现在输出显示上。

7. 发明授权

US06895569B1 IC layout with non-quadrilateral Steiner points 有权
标题翻译：具有非四边形Steiner点的IC布局
公开(公告)号：US06895569B1
公开(公告)日：2005-05-17
申请号：US10066102
申请日：2002-01-31
申请人： Steven Teig , Akira Fujimura , Andrew Caldwell
发明人： Steven Teig , Akira Fujimura , Andrew Caldwell
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ. Some embodiments of the invention provide interconnect lines that have non-rectangular ends. In some embodiments, the interconnect-line ends are partial octagons, hexagons, and/or circles. Also, some embodiments provide Steiner points that are not rectangular. In some embodiments, the Steiner points are octagonal, hexagonal, or circles.
摘要翻译：本发明的一些实施例提供不具有四边形形状的通孔。在一些实施例中，一些或所有通孔的形状为非四边形多边形，例如八边形和六边形。在一些实施例中，一些或所有通孔具有圆形形状。一些实施例提供具有菱形形状的第一组通孔和具有矩形形状的第二组通孔。在一些实施例中，也可以通过金刚石触点和矩形触点形成通孔。钻石接触有四面。在下面描述的实施例中，钻石经过接触的所有四个侧面具有相等的边。然而，在其他实施例中，通孔接触可以是具有比另一对侧长的一对侧面的菱形的形状。类似地，在下面描述的实施例中，矩形通孔触点是具有四个相等边的正方形。然而，在其他实施例中，矩形通孔接触件的长度和宽度可以不同。本发明的一些实施例提供具有非矩形端部的互连线。在一些实施例中，互连线端部是部分八边形，六边形和/或圆形。而且，一些实施例提供了不是矩形的Steiner点。在一些实施例中，Steiner点是八边形，六边形或圆形。

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