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1. 发明授权

US09007801B2 Bipolar-MOS memory circuit 有权
标题翻译：双极MOS存储电路
公开(公告)号：US09007801B2
公开(公告)日：2015-04-14
申请号：US13714499
申请日：2012-12-14
申请人： Daniel Robert Shepard
发明人： Daniel Robert Shepard
IPC分类号： G11C5/06 , H01L29/66 , H03K19/00 , H03K19/094
CPC分类号： H03K19/0013 , G11C5/06 , G11C11/06007 , G11C11/22 , G11C11/4097 , G11C11/412 , H01L29/66234 , H03K19/001 , H03K19/082 , H03K19/094 , H03K19/0948
摘要： Integrated electronic memory devices include control logic and one or more cross point information storage arrays. The cross point storage array(s) include a non-linear conductor proximate to at least one cross point storage location, and the control logic comprises (i) an NMOS type transistor and a PNP type transistor, but not a PMOS type transistor, or (ii) a PMOS type transistor and an NPN type transistor, but not an NMOS type transistor.
摘要翻译：集成电子存储器件包括控制逻辑和一个或多个交叉点信息存储阵列。交叉点存储阵列包括靠近至少一个交叉点存储位置的非线性导体，并且控制逻辑包括（i）NMOS型晶体管和PNP型晶体管，但不是PMOS型晶体管，或（ii）PMOS型晶体管和NPN型晶体管，但不是NMOS型晶体管。

2. 发明授权

US08773881B2 Vertical switch three-dimensional memory array 有权
标题翻译：垂直开关三维记忆阵列
公开(公告)号：US08773881B2
公开(公告)日：2014-07-08
申请号：US12720843
申请日：2010-03-10
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/02
CPC分类号： G11C8/10 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C17/12 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L27/1021 , H01L27/1027 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L29/7827 , H01L29/87 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/144
摘要： Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F2. The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.
摘要翻译：形成存储器件的方法包括在衬底上提供衬底，形成源极，沟道和漏极层，以及将源极，沟道和漏极层图案化成具有小于6F2的横截面积的存储器开关阵列。沟道层具有与源极层的掺杂型不同的掺杂型，漏极层具有与掺杂型沟道层不同的掺杂型。

3. 发明授权

US08526217B2 Low-complexity electronic circuit and methods of forming the same 有权
标题翻译：低复杂度的电子电路及其形成方法
公开(公告)号：US08526217B2
公开(公告)日：2013-09-03
申请号：US13692638
申请日：2012-12-03
申请人： Daniel Shepard
发明人： Daniel Shepard
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.
摘要翻译：诸如锁存器或定序器的电子电路包括多个晶体管，所有晶体管都是NMOS晶体管或PMOS晶体管，并且耗散小于或大致相等量的功率作为等效CMOS电路。

4. 发明授权

US08378456B1 Unified switch array for memory devices 有权
标题翻译：用于存储设备的统一交换机阵列
公开(公告)号：US08378456B1
公开(公告)日：2013-02-19
申请号：US13199437
申请日：2011-08-30
申请人： Daniel Robert Shepard
发明人： Daniel Robert Shepard
IPC分类号： H01L29/02
CPC分类号： H01L27/2445 , H01L27/1026 , H01L27/11206 , H01L27/226 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： An array of vertically constructed, electronic switches is disclosed having three, four or more contacts and having a common bottom contact and a plurality of common middle contacts. This switch array will find use in memory devices or display devices.
摘要翻译：公开了一种垂直构造的电子开关阵列，其具有三个，四个或更多个触点并且具有共同的底部触点和多个公共中间触点。该开关阵列将用于存储器件或显示器件。

5. 发明授权

US08358526B2 Diagonal connection storage array 有权
标题翻译：对角线连接存储阵列
公开(公告)号：US08358526B2
公开(公告)日：2013-01-22
申请号：US12395071
申请日：2009-02-27
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/14
摘要： In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
摘要翻译：在一个方面，电子存储器阵列包括重叠的，大致平行的导体组，并且包括在每个重叠点附近的存储元件。一组导体具有不可忽视的阻力。每个存储元件的地址路径遍及第一组和第二组导体中的每一个的一部分以及可选择的电阻元件。所有存储元件地址路径在对应的存储元件上具有基本相等的电压降。

6. 再颁专利

USRE42310E1 Dual-addressed rectifier storage device 审中-公开
标题翻译：双路整流存储设备
公开(公告)号：USRE42310E1
公开(公告)日：2011-04-26
申请号：US11780220
申请日：2007-07-19
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C11/36 , G11C17/06
CPC分类号： G11C17/10 , G06F17/00 , G11C8/04 , G11C17/00 , G11C17/06 , H01L27/1021 , H01L27/112
摘要： A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.
摘要翻译：提供了只读数据存储和检索装置，其没有移动部件并且需要非常低的功率。可以顺序完成寻址，其中地址自动增加或可以随机完成。通过使用在两个坐标方向上寻址的高度对称的二极管矩阵来实现高密度存储; 其对称性使得双寻址整流器存储（DRS）阵列非常可扩展，特别是当作为集成电路时。为了获得更大的存储灵活性，可将多个数字整流器存储阵列并入设备中，其中一个或多个可以被制造为可移除和可互换的。

7. 发明授权

US07813157B2 Non-linear conductor memory 有权
标题翻译：非线性导体存储器
公开(公告)号：US07813157B2
公开(公告)日：2010-10-12
申请号：US11926778
申请日：2007-10-29
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C17/06 , G11C11/00 , G11C17/18
CPC分类号： G11C8/10 , G11C13/02
摘要： A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.
摘要翻译：高速，低功率存储器件包括非线性导体阵列，其中存储，地址解码和输出检测全部由二极管或其它非线性导体完成。在各种实施例中，行和列电阻器可以在连接到未选择的行或列之间的高电阻之间切换，并且当连接到所选择的行和列时可以是低电阻。

8. 发明申请

US20100149865A1 SCR MATRIX STORAGE DEVICE 有权
标题翻译： SCR矩阵存储器件
公开(公告)号：US20100149865A1
公开(公告)日：2010-06-17
申请号：US12633171
申请日：2009-12-08
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C11/36 , H01L21/82
CPC分类号： G11C17/06 , Y10T29/49002
摘要： One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others.
摘要翻译：数据存储设备的最简单形式之一是二极管阵列存储设备。然而，二极管阵列存储器件的问题在于，随着阵列的尺寸增加，连接在阵列的给定选定行或列之间的非寻址二极管的数量和阵列的未寻址列或行的数量分别为，也变得非常大。虽然通过所选行或列上的任何一个非寻址二极管的漏电流对器件的操作几乎没有影响，但通过数千个非寻址二极管的累积泄漏可能变得显着。该累积漏电流可以变得足够大，使得可以移位输出电压，使得用于区分寻址二极管位置的一个状态和零状态的阈值可能变得模糊，并且可能导致寻址的二极管位置的误读。本发明是一种管理二极管阵列存储装置中的漏电流的手段。这是通过主动地改变存储阵列中的二极管的正向电压来实现的，使得连接到所选行线但不连接到所选列线的二极管处于其高阻抗状态，并且连接到所选列的二极管但是没有连接到所选择的行线处于其高阻抗状态; 只有连接到所选行线和所选列线的二极管将切换到其低阻抗状态。本发明是对所有类型的二极管阵列或其它非线性导电元件的阵列的增强，包括：存储设备，可编程逻辑器件，显示阵列，传感器阵列等等。

9. 发明授权

US07593246B2 Low cost high density rectifier matrix memory 失效
标题翻译：低成本高密度整流矩阵存储器
公开(公告)号：US07593246B2
公开(公告)日：2009-09-22
申请号：US11780916
申请日：2007-07-20
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G06K5/04 , G11C5/025 , G11C7/00 , G11C16/04 , G11C29/006 , G11C29/02 , G11C29/025 , G11C2029/5006 , H01L21/84 , H01L22/32 , H01L27/10 , H01L27/105 , H01L27/1052 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
摘要翻译：三维地制造高密度存储器件。为了使故障点保持低电平，地址解码电路被包括在每个层内，使得除了功率和数据线之外，只有地址信号线需要在层之间互连。

10. 发明申请

US20150050788A1 Current steering element formation for memory arrays 审中-公开
标题翻译：用于存储器阵列的当前转向元件形成
公开(公告)号：US20150050788A1
公开(公告)日：2015-02-19
申请号：US13385371
申请日：2012-02-15
申请人： Contour Semiconductor, Inc.
发明人： Daniel Robert Shepard
IPC分类号： H01L45/00 , H01L21/265 , H01L21/306 , H01L27/24 , H01L29/66
CPC分类号： H01L21/2654 , H01L21/26513 , H01L21/76224 , H01L27/2409 , H01L27/2436 , H01L29/8613 , H01L41/06 , H01L45/1683
摘要： The present invention is a method for forming a self-aligned, three dimensional structure in a crystalline surface and then converting that self-aligned, three dimensional structure into an array of diodes or current switches so as to minimize reverse leakage in the resulting array.
摘要翻译：本发明是一种用于在晶体表面形成自对准的三维结构，然后将该自对准的三维结构转换为二极管阵列或电流开关的方法，以便最小化所得阵列中的反向泄漏。

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