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1. 发明申请

US20130010628A1 SYSTEM AND METHOD FOR COOPERATIVE DATA TRANSFER 有权
标题翻译：合作数据传输的系统和方法
公开(公告)号：US20130010628A1
公开(公告)日：2013-01-10
申请号：US13617708
申请日：2012-09-14
申请人： Dorin Viorel , Masato Okuda , Kevin Power , Luciano Sarperi
发明人： Dorin Viorel , Masato Okuda , Kevin Power , Luciano Sarperi
IPC分类号： H04W24/00
CPC分类号： H04B7/022
摘要： A method for cooperative data transfer includes establishing a primary wireless connection with a primary access station. The primary wireless connection uses a primary synchronization channel that is transmitted during a first frame of a super frame. The super frame comprises a plurality of frames. The method also includes detecting a secondary synchronization channel generated by an alternate access station during a subsequent frame of the super frame. The method further includes determining whether the detected secondary synchronization channel has a signal strength greater than a threshold signal strength. The method additionally includes receiving permission to begin a cooperative data transfer operation with both the primary access station and the alternate access station.
摘要翻译：用于协作数据传输的方法包括建立与主接入站的主无线连接。主要无线连接使用在超帧的第一帧期间发送的主同步信道。超帧包括多个帧。该方法还包括在超帧的后续帧期间检测由备用接入站产生的辅同步信道。该方法还包括确定检测到的辅同步信道是否具有大于阈值信号强度的信号强度。该方法还包括接收许可以开始与主接入站和备用接入站的协作数据传输操作。

2. 发明申请

US20100257310A1 MEMORY ACCESS DEVICE, MEMORY ACCESS SYSTEM, AND PROCESSING METHOD OF MEMORY ACCESS DEVICE 有权
标题翻译：存储器访问设备，存储器访问系统和存储器访问设备的处理方法
公开(公告)号：US20100257310A1
公开(公告)日：2010-10-07
申请号：US12752924
申请日：2010-04-01
申请人： Shigeyasu MURASE , Ayuko Uchida , Akio Kanzaki
发明人： Shigeyasu MURASE , Ayuko Uchida , Akio Kanzaki
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , Y02D10/14
摘要： There is provided a memory access device including: a counter counting based on a value holding a size of data corresponding to a processing region requested from a processor; a second memory coupled between the processor and a first memory where the data corresponding to the processing region is stored; a detector detecting a state of the second memory based on a read pointer and a value of the counter in the second memory; and a controller outputting a transfer request to transfer the data corresponding to the processing region from the first memory to the second memory based on a detection result of the detector.
摘要翻译：提供一种存储器访问装置，包括：基于保存与从处理器请求的处理区域相对应的数据的大小的值的计数器; 耦合在所述处理器和存储与所述处理区域对应的数据的第一存储器之间的第二存储器; 基于读取指针检测第二存储器的状态的检测器和第二存储器中的计数器的值; 以及控制器，其基于检测器的检测结果，输出将从处理区域对应的数据从第一存储器传送到第二存储器的传送请求。

3. 发明申请

US20100255614A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100255614A1
公开(公告)日：2010-10-07
申请号：US12817796
申请日：2010-06-17
申请人： Toshiya UCHIDA
发明人： Toshiya UCHIDA
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G01R31/2884 , H01L22/32 , H01L24/73 , H01L25/0652 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01079 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/05552
摘要： In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.
摘要翻译：在由堆叠的半导体芯片构成的半导体器件中，为了独立地测试每个芯片，第二芯片设置为面对第一芯片，其第二互连端连接到第一芯片的第一互连端子。第一和第二芯片的第一和第二外部端子形成在第一和第二芯片的表面上，该表面位于第一和第二芯片的同一侧。因此，即使在第一芯片和第二芯片被粘贴在一起之后，也可以独立地操作第一芯片和第二芯片来测试第一芯片和第二芯片。此外，由于可以将测试探针等与第一芯片和第二芯片的外部端子从同一侧接触，因此可以同时测试第一芯片和第二芯片。

4. 发明申请

US20100251022A1 INTEGRATED CIRCUIT, DEBUGGING CIRCUIT, AND DEBUGGING COMMAND CONTROL METHOD 有权
标题翻译：集成电路，调试电路和调试命令控制方法
公开(公告)号：US20100251022A1
公开(公告)日：2010-09-30
申请号：US12729864
申请日：2010-03-23
申请人： Shuhei SATO , Takashi Sato
发明人： Shuhei SATO , Takashi Sato
IPC分类号： G06F11/27
CPC分类号： G06F13/28 , G06F11/362 , G06F11/3648
摘要： An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.
摘要翻译：集成电路包括总线; 处理单元，被配置为执行用户程序; 以及连接到所述总线的调试电路，所述调试电路响应于来自所述处理单元的命令传送请求，经由所述总线将命令寄存器中的命令传送到所述处理单元，其中，当所述处理单元停止所述用户的执行时程序并向调试电路请求命令传送请求，调试电路在命令传送请求和命令传送操作之间的时间段内对处理单元释放总线的使用权进行响应。

5. 发明申请

US20100237841A1 POWER SUPPLY AND POWER CONTROL DEVICE 有权
标题翻译：电源和电源控制装置
公开(公告)号：US20100237841A1
公开(公告)日：2010-09-23
申请号：US12716133
申请日：2010-03-02
申请人： Yoshihiko MATSUO , Takeshi Kimura , Osamu Takahashi
发明人： Yoshihiko MATSUO , Takeshi Kimura , Osamu Takahashi
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A power supply includes a first switch and a second switch coupled in series between an input voltage terminal to which an input voltage is applied and a reference voltage terminal to which a reference voltage lower than the input voltage is applied, an inductor disposed between a junction coupling the first and second switches and an output terminal from which an output voltage is output, and a controller controlling the first and second switches to be alternately switched at a given switching cycle depending on an error of the output voltage with respect to a target voltage, wherein the controller changes the switching cycle from a first cycle to a second cycle longer than the first cycle, depending on a voltage at the junction when the second switch is in a turned-on state.
摘要翻译：电源包括串联耦合在施加输入电压的输入电压端子与施加了低于输入电压的参考电压的参考电压端子之间的第一开关和第二开关，设置在连接点之间的电感器耦合第一和第二开关以及从其输出输出电压的输出端子，以及控制器，用于根据输出电压相对于目标电压的误差控制第一和第二开关以给定的开关周期交替切换其中，当所述第二开关处于导通状态时，所述控制器将所述开关周期从第一周期改变为比所述第一周期长的第二周期。

6. 发明申请

US20100232530A1 COMMUNICATION APPARATUS 审中-公开
标题翻译：通讯设备
公开(公告)号：US20100232530A1
公开(公告)日：2010-09-16
申请号：US12717656
申请日：2010-03-04
申请人： Norikazu EBISAWA , Satoru Abe
发明人： Norikazu EBISAWA , Satoru Abe
IPC分类号： H04L27/28
CPC分类号： H04L27/3863 , H04L25/06 , H04L27/3809
摘要： A communication apparatus includes a transmitter for transmitting an outgoing radio signal, a receiver for receiving an incoming radio signal, and a controller for controlling a direct current carrier leakage, and the transmitter includes a first multiplier for multiplying a first carrier-wave signal by an In-phase signal, a second multiplier for multiplying a signal having the similar frequency as and a phase shifted by 90 degree with respect to the first carrier-wave signal by a Quadrature-phase signal, and a transmitting amplifier for amplifying a composite signal multiplied by the In-phase signal and the Quadrature-phase signal, respectively, and outputting the composite signal for forming the outgoing radio signal.
摘要翻译：通信装置包括用于发送出射无线电信号的发射机，用于接收输入无线电信号的接收机和用于控制直流载波泄漏的控制器，并且发射机包括第一乘法器，用于将第一载波信号乘以同相信号，用于将具有相似频率的信号相对于第一载波信号相位偏移90度的信号乘以正交相位信号的第二乘法器和用于放大复合信号的发送放大器分别由同相信号和正交相位信号输出，并输出用于形成输出无线电信号的复合信号。

7. 发明申请

US20100224997A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100224997A1
公开(公告)日：2010-09-09
申请号：US12715826
申请日：2010-03-02
申请人： Noriaki Saito , Toyoji Sawada
发明人： Noriaki Saito , Toyoji Sawada
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/53223 , H01L22/32 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0392 , H01L2224/05083 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2224/45144 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.
摘要翻译：半导体器件包括设置在半导体衬底上的第一金属层; 设置在所述第一金属层上的绝缘层; 以及设置在绝缘层上并具有暴露于外部的电极焊盘表面的第二金属层，其中在所述绝缘层和所述第二金属层中设置有凹部; 并且至少第二金属层设置在绝缘层的凹部中。

8. 发明申请

US20100224921A1 SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR 有权
标题翻译：包括电容器的半导体器件
公开(公告)号：US20100224921A1
公开(公告)日：2010-09-09
申请号：US12722115
申请日：2010-03-11
申请人： Wensheng Wang
发明人： Wensheng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/11502 , H01L21/32051 , H01L21/76826 , H01L21/76841 , H01L21/76883 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.
摘要翻译：半导体器件包括形成在覆盖形成在半导体衬底上的MOS晶体管的下层间绝缘膜之上的铁电电容器，包括下电极，氧化物铁电膜，由具有化学计量组成AOx1的导电氧化物制成的第一上电极和实际组成AOx2，具有化学计量组成BOy1的导电氧化物和实施组成BOy2的第二上电极，其中y2 / y1> x2 / x1，以及含有铂族金属组成的第三上电极; 以及形成在下层铁电电容器上方的多层布线结构，并且包括层间绝缘膜和布线。可以防止当铁电电容器的上电极由氧化度低的导电氧化物膜和具有高氧化度的导电氧化物膜制成时可能发生异常生长和氧空位。

9. 发明申请

US20100218057A1 CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路与半导体集成电路的控制方法
公开(公告)号：US20100218057A1
公开(公告)日：2010-08-26
申请号：US12643874
申请日：2009-12-21
申请人： Takashi MAKI , Daisuke Tsukuda , Tetsuya Hiramatsu
发明人： Takashi MAKI , Daisuke Tsukuda , Tetsuya Hiramatsu
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/14 , G11C29/12015 , G11C2029/0405
摘要： A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.
摘要翻译：半导体集成电路包括自检电路，其中当自检电路的操作模式从低速操作模式切换到高速操作模式时，在高速操作中执行处理模式，并且处理结果基于控制信号无效。

10. 发明申请

US20100208978A1 METHOD OF INSPECTING MASK PATTERN AND MASK PATTERN INSPECTION APPARATUS 有权
标题翻译：检查掩模图案和掩模图案检查装置的方法
公开(公告)号：US20100208978A1
公开(公告)日：2010-08-19
申请号：US12708041
申请日：2010-02-18
申请人： Tsuneo TERASAWA , Toshihiko TANAKA , Hiroyuki SHIGEMURA , Hajime AOYAMA , Osamu SUGA
发明人： Tsuneo TERASAWA , Toshihiko TANAKA , Hiroyuki SHIGEMURA , Hajime AOYAMA , Osamu SUGA
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , B82Y10/00 , B82Y40/00 , G01N21/956 , G03F1/24 , G03F1/84 , G03F7/70941 , G06T7/0006 , G06T2207/30148
摘要： A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.
摘要翻译：捕获芯片A的检查图像数据，并且从地图存储块适当地加载表示对应于芯片A的闪光的校正量的数据。接下来，捕获芯片A'的检查图像，并且表示与芯片A'相对应的闪光量的校正量的数据从闪光图存储块加载为轮廓的边缘的移位量模式。通过作为校正数据生成器的校正数据生成块将修正量转换为提供校正数据的图案的几何校正量。在比较块中，对由校正数据生成块生成的闪光的校正量进行比较和修正两个芯片的几何图像，从而判断是否存在缺陷。

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