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1. 发明授权

US12038852B2 Partial logical-to-physical (L2P) address translation table for multiple namespaces 有权
公开(公告)号：US12038852B2
公开(公告)日：2024-07-16
申请号：US17854248
申请日：2022-06-30
申请人： Innogrit Technologies Co., Ltd.
发明人： Bo Fu , Lin Chen , Jie Chen , Cheng-Yun Hsu
IPC分类号： G06F12/109 , G06F12/1009
CPC分类号： G06F12/109 , G06F12/1009 , G06F2212/657
摘要： Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.

2. 发明公开

US20240202084A1 CACHE PROGRAM WITH BACKUP BLOCKS 审中-公开
公开(公告)号：US20240202084A1
公开(公告)日：2024-06-20
申请号：US18587706
申请日：2024-02-26
申请人： InnoGrit Technologies Co., Ltd.
发明人： Gang Zhao , Lin Chen , Jie Chen , Qun ZHAO
IPC分类号： G06F11/20 , G06F3/06
CPC分类号： G06F11/2087 , G06F3/0619 , G06F3/064 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F2201/85
摘要： Systems, apparatus and methods are provided for performing cache program operations in a non-volatile storage system. A method may comprise issuing a first cache program operation from a storage controller to a non-volatile storage device to write data to a first regular block, writing the data to the first regular block and a copy of the data to a backup block, determining that a program error has occurred while writing the data to the first regular block, asserting the program error to the storage controller, retrieving a mapping between the first regular block and the backup block, issuing a read operation to read the copy of the data from the backup block, reading the copy of the data from the backup block and issuing a second cache program operation to write the data to a second regular block and marking the first regular block as defective.

3. 发明授权

US11966585B2 Storage device and storage system 有权
公开(公告)号：US11966585B2
公开(公告)日：2024-04-23
申请号：US17975816
申请日：2022-10-28
申请人： INNOGRIT TECHNOLOGIES CO., LTD.
发明人： Tianren Li , Gang Hu
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0659 , G06F3/0679
摘要： The present disclosure relates to a storage device and a storage system. The device comprises a storage, a storage controller, a control module, and a buffer module. The control module is configured to: when receiving a data read-write instruction, update the data read-write instruction by using a virtual address; apply for K buffer units in the buffer module; perform a write operation on the K buffer units by using data to be read and written; and when any of the K buffer units is full, directly start data transmission of the full buffer unit. By using the virtual storage address and by employing data block management, the present disclosure can update and forward an NVMe I/O command without applying for a storage space in advance, and can start data block transmission without checking the completion message.

4. 发明公开

US20240086089A1 SYSTEM AND METHOD FOR MANAGING SOLID STATE STORAGE DEVICES IN LOW TEMPERATURE ENVIRONMENT 审中-公开
公开(公告)号：US20240086089A1
公开(公告)日：2024-03-14
申请号：US18516913
申请日：2023-11-21
申请人： InnoGrit Technologies Co., Ltd.
发明人： Lin CHEN , Gang ZHAO , Wei JIANG , Zining WU
IPC分类号： G06F3/06 , G06F1/20
CPC分类号： G06F3/0625 , G06F1/206 , G06F3/0653 , G06F3/0679
摘要： Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

5. 发明公开

US20240014830A1 SOFT DECODING CORRECTABLE PAGE ASSISTED LLR ESTIMATION 审中-公开
公开(公告)号：US20240014830A1
公开(公告)日：2024-01-11
申请号：US17858408
申请日：2022-07-06
申请人： Innogrit Technologies Co., Ltd.
发明人： Chenrong XIONG , Jie CHEN
IPC分类号： H03M13/11
CPC分类号： H03M13/1125
摘要： Systems and methods are provided for estimating LLR values used for soft decoding of data stored in non-volatile storage devices. A method may include reading data stored in a non-volatile storage device using a group of soft read reference voltages, decoding the data read from the non-volatile storage device in a soft decoding process, obtaining a number of ones and a number of zeros for each zone of a plurality of zones delineated by the group of soft read reference voltages and obtaining a log-likelihood ratios (LLR) for each zone of the plurality of zones based on a ratio of the number of ones to the number of zeros in each zone.

6. 发明公开

US20230297282A1 DATA WRITING METHOD AND APPARATUS, AND STORAGE MEDIUM 审中-公开
公开(公告)号：US20230297282A1
公开(公告)日：2023-09-21
申请号：US17831126
申请日：2022-06-02
申请人： INNOGRIT TECHNOLOGIES CO., LTD.
发明人： Tao WEI , Zhengtian FENG , Ke WEI
IPC分类号： G06F3/06 , G11C8/08
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0679 , G11C8/08
摘要： The present disclosure relates to a data writing method and apparatus of a NAND flash, and a storage medium. The method includes: for each channel in the NAND flash, pairing all logic units, namely LUNs, in the channel so that each LUN pair includes at least two LUNs; and for each LUN pair, sequentially writing data to one same page in a plurality of pages corresponding to a program mode included in each word line of each LUN in the LUN pair, and after completing data writing to the same page of the word line of all the LUNs in the LUN pair, sequentially writing data to a next same page in the plurality of pages of the word line of each LUN in the LUN pair, until the data writing is sequentially performed on a last same page in the plurality of pages of the word line of each LUN in the LUN pair. Therefore, the transmission efficiency of a NAND bus can be improved, and the data writing performance of the NAND flash can be improved.

7. 发明申请

US20230137668A1 storage device and storage system 有权
公开(公告)号：US20230137668A1
公开(公告)日：2023-05-04
申请号：US17975816
申请日：2022-10-28
申请人： INNOGRIT TECHNOLOGIES CO., LTD.
发明人： Tianren LI , Gang HU
IPC分类号： G06F3/06
摘要： The present disclosure relates to a storage device and a storage system. The device comprises a storage, a storage controller, a control module, and a buffer module. The control module is configured to: when receiving a data read-write instruction, update the data read-write instruction by using a virtual address; apply for K buffer units in the buffer module; perform a write operation on the K buffer units by using data to be read and written; and when any of the K buffer units is full, directly start data transmission of the full buffer unit. By using the virtual storage address and by employing data block management, the present disclosure can update and forward an NVMe I/O command without applying for a storage space in advance, and can start data block transmission without checking the completion message, which optimizes the data processing procedure, reduces the storage time of data in the local buffer, lowers the storage server's requirement for memory, and also reduces the completion latency of the NVMe I/O command.

8. 发明申请

US20230119770A1 TEMPERATURE SENSOR CIRCUIT 有权
公开(公告)号：US20230119770A1
公开(公告)日：2023-04-20
申请号：US17537679
申请日：2021-11-30
申请人： INNOGRIT TECHNOLOGIES CO., LTD.
发明人： Chi CAO , Guanyu QIAN , Kangmin HU
IPC分类号： G01K7/18
摘要： A temperature sensor circuits includes a temperature sensing module, a current generator, a current controlled oscillator, and a counter. The temperature sensing module is sensitive to temperature changes. The current generator respectively generates a positive temperature coefficient current positively related to temperature and a negative temperature coefficient current negatively related to temperature according to the temperature sensed by the temperature induction module. The current controlled oscillator oscillates according to the positive and the negative temperature coefficient currents respectively and outputs a positive and negative temperature coefficient oscillation signals. The counter receives a clock signal and calculates a first period accumulation number of the negative temperature coefficient oscillation signal and a second period accumulation number of the positive temperature coefficient oscillation signal in the same number of clock periods respectively, and acquires a temperature value based on the period accumulation numbers.

9. 发明申请

US20230080105A1 NON-VOLATILE STORAGE CONTROLLER WITH PARTIAL LOGICAL-TO-PHYSICAL (L2P) ADDRESS TRANSLATION TABLE 有权
公开(公告)号：US20230080105A1
公开(公告)日：2023-03-16
申请号：US18057726
申请日：2022-11-21
申请人： Innogrit Technologies Co., Ltd.
发明人： Bo FU , Chi-Chun LAI , Jie CHEN , Dishi LAI , Jian WU , Cheng-Yun HSU , Qian CHENG
IPC分类号： G06F12/1045 , G06F12/0802
摘要： Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

10. 发明申请

US20230014058A1 EMULATION TEST SYSTEM FOR FLASH TRANSLATION LAYER AND METHOD THEREOF 有权
公开(公告)号：US20230014058A1
公开(公告)日：2023-01-19
申请号：US17555130
申请日：2021-12-17
申请人： INNOGRIT TECHNOLOGIES CO., LTD.
发明人： Wentao SHEN , Ke WEI
IPC分类号： G06F3/06 , G06F12/02
摘要： The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

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