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1. 发明申请

US20220012843A1 GRAPHICS ANTI-ALIASING RESOLVE WITH STENCIL MASK 有权
公开(公告)号：US20220012843A1
公开(公告)日：2022-01-13
申请号：US17484925
申请日：2021-09-24
申请人： Intel Coporation
发明人： Hugues Labbe , Tomer Bar-On , Kai Xiao , Ankur N. Shah , John G. Gierach
IPC分类号： G06T1/20 , G06T15/80
摘要： An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

2. 发明申请

US20210272230A1 PRE-PASS SURFACE ANALYSIS TO ACHIEVE ADAPTIVE ANTI-ALIASING MODES 有权
公开(公告)号：US20210272230A1
公开(公告)日：2021-09-02
申请号：US17145973
申请日：2021-01-11
申请人： Intel Coporation
发明人： Abhishek R. Appu , Joydeep Ray , Peter L. Doyle , Subramaniam Maiyuran , Devan Burke , Philip R. Laws , ElMoustapha Ould-Ahmed-Vall , Altug Koker
IPC分类号： G06T1/20 , G06T1/60
摘要： Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

3. 发明授权

US09628152B2 Signal detection method and apparatus in MIMO communication system 有权
公开(公告)号：US09628152B2
公开(公告)日：2017-04-18
申请号：US14849668
申请日：2015-09-10
申请人： Intel Corporation
发明人： Jian Gu , Fei-Feng Xu
IPC分类号： H04B7/04 , H04B7/0413 , H04L1/00 , H04L1/18
CPC分类号： H04B7/0413 , H04L1/0054 , H04L1/1812 , H04L25/03891
摘要： A method for detecting a signal, used in a multi-input multi-output (MIMO) communications system, including: receiving a vector associated with data bits transmitted from the MIMO communications system; finding a first layer from the received vector according to a determining condition, wherein the received vector includes multiple layers, and the multiple layers include the first layer and remaining layers; performing a first scanning procedure for the multiple layers of the received vector to obtain log likelihood ratios (LLR) corresponding to the data bits transmitted from the remaining layers; obtaining a received vector of the first layer according to an equivalent received vector of the remaining layers; and performing a second scanning procedure on data bits of the first layer according to the received vector of the first layer to generate an LLR corresponding to the data bits of the first layer.

4. 发明授权

US09373306B2 Direct viewer projection 有权
标题翻译：直接观看者投影
公开(公告)号：US09373306B2
公开(公告)日：2016-06-21
申请号：US14224669
申请日：2014-03-25
申请人： INTEL CORPORATION
发明人： Maynard C. Falconer , Nathan R. Andrysco
IPC分类号： G09G5/10 , G09G3/20 , G09G3/06 , G09G3/36 , G06T11/00 , G09F9/00 , G02F1/13 , H05B33/00
CPC分类号： G09G5/10 , G09G3/003 , G09G3/2085 , G09G2300/0814 , G09G2320/0233 , G09G2320/0646 , G09G2320/0653 , G09G2358/00 , H04N13/32 , H04N13/363 , H04N13/368 , H04N2013/403 , H04N2013/405
摘要： Techniques are disclosed for direct viewer projection, which involves having each pixel's emitted light aimed at or otherwise provided directly to the target pupil of a viewing person. In one embodiment, the techniques are implemented using steerable, collimated light sources fashioned into an array to effectively provide a display screen. Each steerable, collimated light source of the array corresponds to one pixel of a given image at a given viewing location, such that no one light source shows a whole image; rather, the whole array is used to display an image. The array can be scanned to provide different images to different viewing locations. The content projected to the different locations may be related (e.g., a movie) or unrelated (e.g., two different movies). A specific viewer can be identified and tracked such that the content is only projected to the target viewer's eyes and no one else's.
摘要翻译：公开了用于直接观看者投影的技术，其涉及将每个像素的发射光瞄准或以其他方式直接提供给观看者的目标瞳孔。在一个实施例中，使用形成阵列的可导向的准直光源实现技术以有效地提供显示屏。阵列的每个可导向的准直光源对应于在给定观看位置处的给定图像的一个像素，使得没有一个光源显示整个图像; 相反，整个数组用于显示图像。可以扫描阵列以向不同的观看位置提供不同的图像。投影到不同位置的内容可以是相关的（例如，电影）或不相关的（例如，两个不同的电影）。可以识别和跟踪特定的观看者，使得内容仅被投射到目标观众的眼睛，而不是其他人。

5. 发明授权

US08987794B2 Non-planar gate all-around device and method of fabrication thereof 有权
标题翻译：非平面栅极全能器件及其制造方法
公开(公告)号：US08987794B2
公开(公告)日：2015-03-24
申请号：US13997118
申请日：2011-12-23
申请人： Willy Rachmady , Ravi Pillarisetty , Van H. Le , Jack T. Kavalieros , Robert S. Chau , Jessica S. Kachian
发明人： Willy Rachmady , Ravi Pillarisetty , Van H. Le , Jack T. Kavalieros , Robert S. Chau , Jessica S. Kachian
IPC分类号： H01L21/336 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/78 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/0669 , H01L29/0673 , H01L29/1033 , H01L29/165 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/7851 , H01L29/78618 , H01L29/78696 , H01L2029/7858
摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.
摘要翻译：描述了非平面栅极全面器件及其制造方法。在一个实施例中，该器件包括具有第一晶格常数的顶表面的衬底。嵌入的epi源极和漏极区域形成在衬底的顶表面上。嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。在一个实施例中，第二晶格常数和第三晶格常数不同于第一晶格常数。通道纳米线包括最底部的沟道纳米线，并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。在每个通道纳米线上形成栅极电介质层。在栅极电介质层上形成栅电极并围绕每个沟道纳米线。

6. 发明授权

US07849334B2 Transitioning a computing platform to a low power system state 有权
标题翻译：将计算平台转换为低功率系统状态
公开(公告)号：US07849334B2
公开(公告)日：2010-12-07
申请号：US11541222
申请日：2006-09-29
申请人： Dale Juenemann , Paul Diefenbaugh
发明人： Dale Juenemann , Paul Diefenbaugh
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： A method which includes initiating a power management policy based on a processing element for a computing platform entering a given power state. The power management policy includes a determination as to whether an input/output (I/O) controller and a memory controller for the computing platform are substantially quiescent. The computing platform may then be transitioned to a low power system state from a run power system state based on a determination that both the I/O controller and the memory controller are substantially quiescent and an indication that the computing platform is capable of entering the low power system state. According to this method, the low power system state includes entering one or more devices responsive to the computing platform in a power level adequate to retain a configuration state that enables the one or more devices to transition back to the run power system state in a manner that is substantially transparent to an operating system for the computing platform. Other implementations and examples are also described in this disclosure.
摘要翻译：一种方法，其包括基于进入给定功率状态的计算平台的处理元件发起功率管理策略。电源管理策略包括关于计算平台的输入/输出（I / O）控制器和存储器控制器是否基本上是静止的确定。然后，基于确定I / O控制器和存储器控制器基本上是静止的计算平台可以从运行电力系统状态转换到低功率系统状态，以及计算平台能够进入低电平的指示电力系统状态。根据该方法，低功率系统状态包括以足够的功率水平进入响应于计算平台的一个或多个设备，以使得能够以一种或多种设备以一种或多种方式转换回运行电力系统状态的配置状态这对于计算平台的操作系统是基本上透明的。在本公开中还描述了其他实现和示例。

7. 发明申请

US20070190695A1 APPARATUS AND METHOD INTEGRATING AN ELECTRO-OSMOTIC PUMP AND MICROCHANNEL ASSEMBLY INTO A DIE PACKAGE 失效
标题翻译：将电动泵和微通道组件集成在一个DIE包装中的装置和方法
公开(公告)号：US20070190695A1
公开(公告)日：2007-08-16
申请号：US11691124
申请日：2007-03-26
申请人： Alan Myers , R. List , Gilroy Vandentop
发明人： Alan Myers , R. List , Gilroy Vandentop
IPC分类号： H01L21/00
CPC分类号： H01L23/473 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
摘要翻译：一种模具封装以及用于将电渗透泵和微通道冷却组件集成到管芯封装中的方法和装置。

8. 发明授权

US06996749B1 Method and apparatus for providing debug functionality in a buffered memory channel 失效
标题翻译：用于在缓冲存储器通道中提供调试功能的方法和装置
公开(公告)号：US06996749B1
公开(公告)日：2006-02-07
申请号：US10713564
申请日：2003-11-13
申请人： Kuljit S. Bains , Robert M. Ellis , Chris B. Freeman , John B. Halbert , David Zimmerman
发明人： Kuljit S. Bains , Robert M. Ellis , Chris B. Freeman , John B. Halbert , David Zimmerman
IPC分类号： G06F11/00
CPC分类号： G11C29/48 , G11C29/56 , G11C2029/5602
摘要： Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
摘要翻译：本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。在权利要求中描述了其它实施例。

9. 发明授权

US5978946A Methods and apparatus for system testing of processors and computers using signature analysis 失效
标题翻译：使用签名分析对处理器和计算机进行系统测试的方法和装置
公开(公告)号：US5978946A
公开(公告)日：1999-11-02
申请号：US962160
申请日：1997-10-31
申请人： Wayne Maurice Needham
发明人： Wayne Maurice Needham
IPC分类号： G06F11/267 , G11C29/40 , G01R31/28
CPC分类号： G06F11/2236 , G11C29/40
摘要： In one aspect of the present invention, an apparatus is provided for testing a processor running a software program. The apparatus includes a bus having control, data and address lines and a device assigned at least one address. The bus connects the device to the processor. The apparatus includes a multiple input signature register having a plurality of parallel input terminals connected to the data lines. The apparatus includes a control unit having first and second input terminals connected to the address and control lines respectively. The control unit is adapted to enabling the parallel input terminals of the multiple input signature register in response to detecting on the address and control lines at least one preselected triggering event executed by the software program to a preselected address of the device. The apparatus includes a signature comparator adapted to comparing a test signature number from the multiple input signature register to a reference signature number.
摘要翻译：在本发明的一个方面，提供一种用于测试运行软件程序的处理器的装置。该设备包括具有控制，数据和地址线的总线以及分配至少一个地址的设备。总线将设备连接到处理器。该装置包括具有连接到数据线的多个并行输入端的多输入签名寄存器。该装置包括具有分别连接到地址和控制线的第一和第二输入端的控制单元。所述控制单元适于使所述多输入签名寄存器的并行输入端能够响应于将地址和控制线上至少一个由软件程序执行的预先选择的触发事件检测到设备的预选地址。该装置包括一个签名比较器，适用于将来自多输入签名寄存器的测试签名号与参考签名号进行比较。

10. 发明申请

US20220262957A1 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES 有权
公开(公告)号：US20220262957A1
公开(公告)日：2022-08-18
申请号：US17737882
申请日：2022-05-05
申请人： Intel Coporation
发明人： Biswajeet GUHA , Mauro J. KOBRINSKY , Tahir GHANI
IPC分类号： H01L29/786 , H01L29/423 , H01L27/088 , H01L21/8234 , H01L29/06
摘要： Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

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