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1. 发明授权

US09613863B2 Method for forming electroless metal through via 有权
公开(公告)号：US09613863B2
公开(公告)日：2017-04-04
申请号：US15040148
申请日：2016-02-10
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Henrik Knutsson
IPC分类号： H01L21/44 , H01L21/768 , H01L21/288 , H01L23/48 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/02595 , H01L21/288 , H01L21/76847 , H01L21/76874 , H01L21/76879 , H01L21/76888 , H01L21/76892 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

2. 发明申请

US20150076677A1 CTE MATCHED INTERPOSER AND METHOD OF MAKING 有权
标题翻译： CTE匹配插件及其制作方法
公开(公告)号：US20150076677A1
公开(公告)日：2015-03-19
申请号：US14391855
申请日：2013-04-15
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Daniel Perttu
IPC分类号： H01L23/498 , H01L23/31 , H01L21/48
CPC分类号： H01L23/49838 , H01L21/486 , H01L23/147 , H01L23/3142 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L2224/16 , H01L2924/1461 , H01L2924/00
摘要： The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter,
摘要翻译：本插入器使得可以在非常宽的范围内调整插入件的热膨胀系数以使其附着的部件相匹配。半导体插入器包括具有第一侧和相对的第二侧的半导体材料的衬底。至少有一个导电晶圆通孔包括金属。至少一个凹部设置在衬底的第一侧中，并且在衬底的半导体材料中，凹槽填充有金属并与晶片通孔连接，从而提供布线结构。金属填充的通孔和金属填充的凹部的暴露表面基本上与衬底的第一侧上的衬底表面齐平。晶圆通孔包括窄部分和较宽部分，并且接触元件设置在具有纵横比，高度：直径，<1：1，优选1：1至2：1的布线结构上。

3. 发明申请

US20150054136A1 METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 有权
标题翻译：提供通孔和路由结构的方法
公开(公告)号：US20150054136A1
公开(公告)日：2015-02-26
申请号：US14389592
申请日：2013-03-28
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Daniel Perttu
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76831 , H01L21/2885 , H01L21/76807 , H01L21/7684 , H01L21/76871 , H01L21/76879 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is
摘要翻译：提供通孔和布线结构的方法包括：提供具有设置在晶片表面上的凹陷和盲孔的衬底晶片; 在凹槽和孔中提供绝缘层; 对孔和凹槽进行金属化; 并且去除孔的底部中的氧化物层以提供晶片的背侧和前侧之间的接触。一种半导体器件，包括具有延伸穿过衬底的至少一个金属化通孔的衬底和形成与通孔一起布线的至少一个金属化凹槽。前侧场和后侧场均有氧化层。凹槽和通孔中的金属至少在前侧与场上的氧化物齐平，由此提供平坦的前侧。半导体器件的厚度<300μm。

4. 发明申请

US20140042498A1 STARTING SUBSTRATE FOR SEMICONDUCTOR ENGINEERING HAVING SUBSTRATE-THROUGH CONNECTIONS AND A METHOD FOR MAKING SAME 有权
标题翻译：具有基板贯穿连接的半导体工程的启动基板及其制造方法
公开(公告)号：US20140042498A1
公开(公告)日：2014-02-13
申请号：US14112403
申请日：2012-04-19
申请人： Ulf Erlesand
发明人： Ulf Erlesand
IPC分类号： B81B3/00 , B81C1/00
CPC分类号： B81B3/0086 , B81C1/00222 , H01L21/76898 , H01L23/481 , H01L29/4236 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A substrate-through electrical connection (10) for connecting components on opposite sides of a substrate, and a method for making same. The connection includes a substrate-through via made from substrate material (10′). There is a trench (11) provided surrounding the via, the walls of the trench being coated with a layer of insulating material (12) and the trench (11) is filled with conductive or semi-conductive material (13). A doping region (15) for threshold voltage adjustment is provided in the via material in the surface of the inner trench wall between insulating material (12) and the material (10′) in the via. There are contacts (17′, 17″) to the via on opposite sides of the substrate, and a contact (18) to the conductive material (13) in the trench (11) so as to enable the application of a voltage to the conductive material (13).
摘要翻译：一种用于连接衬底的相对侧上的部件的衬底通电连接（10）及其制造方法。连接包括由衬底材料（10'）制成的衬底通孔。设置有围绕通孔设置的沟槽（11），沟槽的壁涂覆有绝缘材料层（12），并且沟槽（11）填充有导电或半导体材料（13）。用于阈值电压调整的掺杂区域（15）在通孔材料中提供在绝缘材料（12）和通孔中的材料（10'）之间的内沟槽壁的表面中。在基板的相对侧上具有与通孔相接的触点（17'，17“），以及与沟槽（11）中的导电材料（13）的触点（18），以便能够施加电压导电材料（13）。

5. 发明授权

US08630033B2 Via structure and method thereof 有权
标题翻译：其结构及其方法
公开(公告)号：US08630033B2
公开(公告)日：2014-01-14
申请号：US13166621
申请日：2011-06-22
申请人： Thorbjörn Ebefors , Edvard Kälvesten , Peter Agren , Niklas Svedin , Thomas Ericson
发明人： Thorbjörn Ebefors , Edvard Kälvesten , Peter Agren , Niklas Svedin , Thomas Ericson
IPC分类号： G02B26/08
CPC分类号： G02B26/0841 , B81B7/0006 , B81B2201/042 , B81B2201/045 , H01L23/481 , H01L2924/0002 , H02N1/006 , H01L2924/00
摘要： A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
摘要翻译：分层微电子和/或微机械结构包括在导电层之间具有绝缘层的至少三个交替导电层。还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。该装置具有根据本发明的分层结构。还提供了制造这种分层MEMS结构的方法。

6. 发明授权

US08598676B2 Barrier structure 有权
标题翻译：屏障结构
公开(公告)号：US08598676B2
公开(公告)日：2013-12-03
申请号：US13566081
申请日：2012-08-03
申请人： Thorbjörn Ebefors , Tomas Bauer
发明人： Thorbjörn Ebefors , Tomas Bauer
IPC分类号： H01L29/06
CPC分类号： H01L21/762 , B81C1/00246 , H01L21/823481 , H01L23/055 , H01L23/147 , H01L23/26 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L2223/6622 , H01L2223/6688 , H01L2224/16225 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/09701 , H01L2924/1433 , H01L2924/1461 , H01L2924/15153 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.
摘要翻译：半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险，为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。还描述了制造这样的基板的方法，包括在晶片中的蚀刻沟槽，以及用绝缘材料填充沟槽。

7. 发明申请

US20120292736A1 BARRIER STRUCTURE 有权
标题翻译：障碍物结构
公开(公告)号：US20120292736A1
公开(公告)日：2012-11-22
申请号：US13566081
申请日：2012-08-03
申请人： Thorbjörn Ebefors , Tomas Bauer
发明人： Thorbjörn Ebefors , Tomas Bauer
IPC分类号： H01L29/06
CPC分类号： H01L21/762 , B81C1/00246 , H01L21/823481 , H01L23/055 , H01L23/147 , H01L23/26 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L2223/6622 , H01L2223/6688 , H01L2224/16225 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/09701 , H01L2924/1433 , H01L2924/1461 , H01L2924/15153 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.
摘要翻译：半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险，为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。还描述了制造这样的基板的方法，包括在晶片中的蚀刻沟槽，以及用绝缘材料填充沟槽。

8. 发明申请

US20120288422A1 GLASS MICRO FLUIDIC DEVICE 审中-公开
标题翻译：玻璃微流体装置
公开(公告)号：US20120288422A1
公开(公告)日：2012-11-15
申请号：US13469377
申请日：2012-05-11
申请人： Edvard KALVESTEN
发明人： Edvard KALVESTEN
IPC分类号： B81B1/00 , B32B3/20 , C03B23/24
CPC分类号： C03B23/24 , B81B2201/051 , B81B2203/0338 , B81C1/00119 , B81C2203/036 , Y10T428/24562
摘要： A method of making a microfluidic device, includes: providing an optically transparent bottom substrate and an optically transparent top substrate, each made of glass. Recesses are made in the top substrate and the top and bottom substrates are bonded together. Then, material is removed from the top substrate to expose the recesses, and a lid is attached to the top substrate so as to cover the recesses whereby channels are formed. At least that surface of the lid facing towards the recesses in the top substrate has a surface roughness of
摘要翻译：制造微流体装置的方法包括：提供每个由玻璃制成的光学透明的底部基底和光学透明的顶部基底。在顶部基板上形成凹部，顶部和底部基板结合在一起。然后，将材料从顶部基板移除以露出凹部，并且将盖子附接到顶部基板，以覆盖凹部，从而形成通道。至少面向顶部衬底中的凹部的盖的表面具有<5nm，优选<2nm的表面粗糙度。还描述了一种微流体装置，其包括光学透明材料的主体，以及在主体内延伸的至少一个通道，还具有底表面，顶表面和侧壁的通道。顶表面和底表面均表现出粗糙度<5nm，优选<2nm。

9. 发明申请

US20120267773A1 Functional Capping 有权
标题翻译：功能上限
公开(公告)号：US20120267773A1
公开(公告)日：2012-10-25
申请号：US13130264
申请日：2009-11-19
申请人： Thorbjörn Ebefors , Edvard Kälvesten , Tomas Bauer
发明人： Thorbjörn Ebefors , Edvard Kälvesten , Tomas Bauer
IPC分类号： H01L21/768 , H01L23/48 , H01L23/04 , H01L21/60
CPC分类号： H01L21/50 , B81B7/007 , B81B2207/095 , B81C1/00301 , H01L21/6835 , H01L21/76898 , H01L21/78 , H01L23/04 , H01L23/10 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/585 , H01L23/642 , H01L23/645 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L2221/68363 , H01L2221/68372 , H01L2223/6616 , H01L2223/6622 , H01L2223/6655 , H01L2223/6677 , H01L2224/02311 , H01L2224/02313 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05073 , H01L2224/05155 , H01L2224/05548 , H01L2224/05573 , H01L2224/05644 , H01L2224/1146 , H01L2224/13009 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/29009 , H01L2224/29011 , H01L2224/29012 , H01L2224/29018 , H01L2224/29101 , H01L2224/29111 , H01L2224/29144 , H01L2224/30051 , H01L2224/3012 , H01L2224/81005 , H01L2224/81203 , H01L2224/81801 , H01L2224/83005 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/01027 , H01L2924/01028 , H01L2924/3512
摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.
摘要翻译：一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。晶片被接合到另一个承载电子和微电子/机械部件的晶片，使得第一晶片形成覆盖第二晶片的封盖结构。最后，将晶片单个化为单个器件。

10. 发明申请

US20120126392A1 Methods for Making Micro Needles and Applications Thereof 有权
标题翻译：微针制作方法及应用
公开(公告)号：US20120126392A1
公开(公告)日：2012-05-24
申请号：US13278890
申请日：2011-10-21
申请人： Edvard Kälvesten , Thorbjörn Ebefors , Thierry Corman
发明人： Edvard Kälvesten , Thorbjörn Ebefors , Thierry Corman
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： A61M37/0015 , A61B5/053 , A61B5/150022 , A61B5/150282 , A61B5/150984 , A61M2037/003 , A61M2037/0046 , A61M2037/0053 , A61N1/0502 , A61N1/0551 , H01L2224/48091 , H01L2224/8592 , H01L2924/00014
摘要： The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.
摘要翻译：本发明在一般方面涉及在衬底上制造垂直突出元件的方法，所述元件具有包括至少一个倾斜表面的尖端和在所述基底和所述尖端之间延伸的细长主体部分。该方法包括形成所述倾斜表面的各向异性的晶面依赖蚀刻; 以及形成所述细长主体部分的各向异性非晶面依赖蚀刻; 结合限定所述突出元件的合适的图案化工艺具有预定的基部几何形状。

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