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1. 发明授权

US09057763B2 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test 有权
公开(公告)号：US09057763B2
公开(公告)日：2015-06-16
申请号：US14078114
申请日：2013-11-12
申请人： Syntest Technologies, Inc.
发明人： Laung-Terng Wang , Po-Ching Hsu , Shih-Chia Kao , Meng-Chyi Lin , Hsin-Po Wang , Hao-Jan Chao , Xiaqing Wen
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

2. 发明授权

US08335954B2 Method and apparatus for low-pin-count scan compression 失效
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US08335954B2
公开(公告)日：2012-12-18
申请号：US13529686
申请日：2012-06-21
申请人： Nur A. Touba , Laung-Terng Wang , Shianling Wu
发明人： Nur A. Touba , Laung-Terng Wang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

3. 发明授权

US08230282B2 Method and apparatus for low-pin-count scan compression 有权
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US08230282B2
公开(公告)日：2012-07-24
申请号：US13172046
申请日：2011-06-29
申请人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

4. 发明申请

US20120110402A1 METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS 失效
标题翻译：用于测试3D集成电路的方法和装置
公开(公告)号：US20120110402A1
公开(公告)日：2012-05-03
申请号：US13222130
申请日：2011-08-31
申请人： Laung-Terng Wang , Nur Touba , Michael S. Hsiao , Shianling Wu , Zhigang Jiang
发明人： Laung-Terng Wang , Nur Touba , Michael S. Hsiao , Shianling Wu , Zhigang Jiang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558 , G01R31/318572
摘要： A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.
摘要翻译：一种使用时分解复用/复用来测试基于扫描的3D集成电路（3DIC）的方法和装置，其允许在输入/输出焊盘处施加的高数据速率扫描图案转换为应用于每个的低数据速率扫描模式嵌入模块在3DIC。提出了一套3D设计指南，以减少测试次数和预键测试和后绑定测试所需的硅通孔数（TSV）。该技术允许重新开发用于每个管芯（层）的前绑定测试的扫描模式，用于整个3DIC的后绑定测试。它进一步减少测试应用时间，而不用担心I / O焊盘计数限制和故障覆盖损失的风险。

5. 发明授权

US08091002B2 Multiple-capture DFT system to reduce peak capture power during self-test or scan test 失效
标题翻译：多捕捉DFT系统，可在自检或扫描测试期间降低峰值捕获能力
公开(公告)号：US08091002B2
公开(公告)日：2012-01-03
申请号：US12797302
申请日：2010-06-09
申请人： Laung-Terng Wang , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
发明人： Laung-Terng Wang , Shianling Wu , Zhigang Jiang , Jinsong Liu , Hao-Jan Chao , Lizhen Yu , Feifei Zhao , Fangfang Li , Jianping Yan
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31704 , G01R31/318552 , G01R31/318594
摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.
摘要翻译：一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

6. 发明申请

US20110197171A1 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
标题翻译：计算机辅助设计系统，用于自动扫描合成记录级别
公开(公告)号：US20110197171A1
公开(公告)日：2011-08-11
申请号：US13030410
申请日：2011-02-18
申请人： Laung-Terng (L.-T.) WANG , Xiaoqing Wen
发明人： Laung-Terng (L.-T.) WANG , Xiaoqing Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
摘要翻译：一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤和冲洗/随机测试台生成。此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

7. 发明授权

US07735049B2 Mask network design for scan-based integrated circuits 失效
标题翻译：基于扫描的集成电路的掩模网络设计
公开(公告)号：US07735049B2
公开(公告)日：2010-06-08
申请号：US11350949
申请日：2006-02-10
申请人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Boryau (Jack) Sheu
发明人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Boryau (Jack) Sheu
IPC分类号： G06F17/50 , G01R31/3177 , G01R31/3181 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318536
摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
摘要翻译：一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入。还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

8. 发明授权

US07451371B2 Multiple-capture DFT system for scan-based integrated circuits 失效
标题翻译：用于基于扫描的集成电路的多捕捉DFT系统
公开(公告)号：US07451371B2
公开(公告)日：2008-11-11
申请号：US11151258
申请日：2005-06-14
申请人： Laung-Terng Wang , Xiaoqing Wen
发明人： Laung-Terng Wang , Xiaoqing Wen
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/31704 , G01R31/318552 , G01R31/31858
摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
摘要翻译：一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和每个域具有多个扫描单元。该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式，三态总线和低功率门控时钟。

9. 发明申请

US20080276141A1 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit 审中-公开
标题翻译：用于在基于扫描的集成电路中广播扫描图案的方法和装置
公开(公告)号：US20080276141A1
公开(公告)日：2008-11-06
申请号：US12216639
申请日：2008-07-09
申请人： Laung-Terng(L.-T.) Wang , Xiaoqing Wen , Shyh-Horng Lin , Khader S. Abdel-Hafez
发明人： Laung-Terng(L.-T.) Wang , Xiaoqing Wen , Shyh-Horng Lin , Khader S. Abdel-Hafez
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318533 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出方法来重新排列所选扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且合成广播器和压缩器。

10. 发明授权

US07434126B2 Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults 有权
标题翻译：计算机辅助设计（CAD）多捕获DFT系统，用于检测或定位跨时钟域故障
公开(公告)号：US07434126B2
公开(公告)日：2008-10-07
申请号：US11806098
申请日：2007-05-30
申请人： Laung-Terng Wang , Po-Ching Hsu , Xiaoqing Wen
发明人： Laung-Terng Wang , Po-Ching Hsu , Xiaoqing Wen
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318552 , G01R31/318594 , G06F17/5031 , G06F17/505
摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.
摘要翻译：一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有多个扫描单元。该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

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