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1. 发明授权

US10741540B2 Integrated circuit layout method and device 有权
公开(公告)号：US10741540B2
公开(公告)日：2020-08-11
申请号：US16204678
申请日：2018-11-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Ying Chen , Lee-Chung Lu , Li-Chun Tien , Ta-Pen Guo
IPC分类号： H01L27/088 , H01L27/02 , H01L27/092 , G06F30/392
摘要： A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.

2. 发明授权

US07592675B2 Partial FinFET memory cell 有权
标题翻译：部分FinFET存储单元
公开(公告)号：US07592675B2
公开(公告)日：2009-09-22
申请号：US11588483
申请日：2006-10-27
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/092
CPC分类号： H01L27/1108 , H01L27/11 , H01L27/1104 , H01L29/785 , H01L29/7854
摘要： A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate, wherein the NMOS device is a Fin field effect transistor (FinFET).
摘要翻译：半导体结构包括半导体衬底，在半导体衬底的表面处的平面PMOS器件和在半导体衬底的表面处的NMOS器件，其中NMOS器件是Fin场效应晶体管（FinFET）。

3. 发明授权

US09536777B2 Interconnect apparatus and method 有权
标题翻译：互连装置和方法
公开(公告)号：US09536777B2
公开(公告)日：2017-01-03
申请号：US13890841
申请日：2013-05-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jeng-Shyan Lin , Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Shih Pei Chou , Min-Feng Kao , Szu-Ying Chen
IPC分类号： H01L21/768 , H01L23/48 , H01L23/00 , H01L25/00 , H01L27/146 , H01L25/065
CPC分类号： H01L27/14634 , H01L21/30625 , H01L21/768 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L24/09 , H01L24/80 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L27/14636 , H01L27/1464 , H01L27/1469 , H01L2224/08146 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06565 , H01L2924/01322 , H01L2924/12036 , H01L2924/12043 , H01L2924/13056 , H01L2924/1431 , H01L2224/80 , H01L2924/00 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.
摘要翻译：一种方法包括将第二芯片上的第一芯片接合，在第一芯片的非结合侧上沉积第一硬掩模层，在第一硬掩模层上沉积第二硬掩模层，蚀刻第一半导体的第一衬底使用第二硬掩模层作为第一蚀刻掩模，并使用第一硬掩模层作为第二蚀刻掩模蚀刻第一芯片和第二芯片的IMD层。

4. 发明授权

US09449868B2 Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films 有权
标题翻译：通过聚结薄膜纵横比捕获形成半导体二极管的方法
公开(公告)号：US09449868B2
公开(公告)日：2016-09-20
申请号：US14685399
申请日：2015-04-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Anthony J. Lochtefeld
IPC分类号： H01L21/66 , H01L21/762 , H01L21/02 , H01L21/18 , H01L31/18 , H01L33/00 , H01L33/12 , H01L29/15 , H01L29/861 , H01L29/04 , H01L29/88 , H01L33/52
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L21/02647 , H01L21/187 , H01L29/04 , H01L29/151 , H01L29/861 , H01L29/882 , H01L31/1852 , H01L33/007 , H01L33/12 , H01L33/52 , H01L2933/005 , Y02E10/543 , Y02E10/544 , Y02P70/521
摘要： A method of forming a photonic device that comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The method may further include forming a top diode material and an active diode region between the top and bottom diode materials.
摘要翻译：一种形成光子器件的方法，该光子器件包括衬底和介电材料，该电介质材料包括暴露衬底的一部分的两个或更多个开口，所述两个或更多个开口各自具有至少为1的长宽比。与衬底晶格失配的半导体材料占据两个或更多个开口，并且在两个或更多个开口上方聚结形成底部二极管区域。该方法还可以包括在顶部和底部二极管材料之间形成顶部二极管材料和有源二极管区域。

5. 发明申请

US20100328827A1 ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS, INTEGRATED CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF 有权
标题翻译：静电放电（ESD）保护电路，集成电路，系统及其工作方法
公开(公告)号：US20100328827A1
公开(公告)日：2010-12-30
申请号：US12824571
申请日：2010-06-28
申请人： Da-Wei LAI , Wade MA
发明人： Da-Wei LAI , Wade MA
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current minor is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.
摘要翻译：与输入/输出（I / O）接口耦合的静电放电（ESD）保护电路。 ESD保护电路包括耦合在第一电源电压和第二电源电压之间的钳位场效应晶体管（FET）。逆变器包括输入端和输出端。反相器的输出端与钳位FET的栅极耦合。 RC时间常数电路设置在第一电源电压和第二电源电压之间。电流镜包括第一晶体管。电流调节器耦合在逆变器的输入端和第二电源电压之间。电路与逆变器的输入端耦合。该电路能够在逆变器的输入端输出电压状态，该电压状态能够在使用负电流对I / O焊盘进行闩锁测试的同时基本上关断钳位FET。

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