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1. 发明授权

US08434068B2 Development system 有权
标题翻译：开发体系
公开(公告)号：US08434068B2
公开(公告)日：2013-04-30
申请号：US12256938
申请日：2008-10-23
申请人： Michael Thomas Wrighton , Matthew David Fyles , Hendrik Lambertus Muller
发明人： Michael Thomas Wrighton , Matthew David Fyles , Hendrik Lambertus Muller
IPC分类号： G06F9/44
CPC分类号： G06F11/3664 , G06F8/20
摘要： A system comprising: a server; a computer terminal coupled remotely to the server via a network and installed with a web browser; and an external test platform, connected externally to the computer terminal, the test platform comprising a programmable target device and interface circuitry operable to communicate between the computer terminal and the target device. The server hosts a development tool available for download to the web browser via the network. The development tool comprises: one or more applets to be run by the web browser, and one or more web pages for display by the web browser to provide a user-interface for the development tool including to provide access to the one or more applets. The one or more applets at least comprise code-analysis applet software programmed so as when run by the web browser to operate said interface circuitry to: load code to be tested from the computer terminal onto the target device for test operation.
摘要翻译：一种系统，包括：服务器; 计算机终端，经由网络远程耦合到服务器并且安装有网络浏览器; 以及外部测试平台，其外部连接到计算机终端，所述测试平台包括可编程目标设备和可操作以在所述计算机终端与所述目标设备之间通信的接口电路。服务器托管可通过网络下载到Web浏览器的开发工具。开发工具包括：由web浏览器运行的一个或多个小应用程序，以及一个或多个网页，用于由web浏览器显示以提供用于开发工具的用户界面，包括提供对一个或多个小应用程序的访问。所述一个或多个小应用程序至少包括代码分析小应用软件，其被编程为当由web浏览器运行时操作所述接口电路：将要测试的代码从计算机终端加载到目标设备上用于测试操作。

2. 发明申请

US20110225570A1 PROGRAM FLOW ROUTE CONSTRUCTOR 有权
标题翻译：程序流程路由器
公开(公告)号：US20110225570A1
公开(公告)日：2011-09-15
申请号：US12723444
申请日：2010-03-12
申请人： Andrew STANFORD-JASON
发明人： Andrew STANFORD-JASON
IPC分类号： G06F11/36 , G06F9/45
CPC分类号： G06F11/3604
摘要： A method and corresponding tool, the method comprising: receiving as an input (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes; and (b) an indication of at least one start and end instruction. The method further comprises probing the levels of the higher-level structure to extract a substructure representing a route through the program from the start to the end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes; and based on the extracted substructure, estimating an execution time for the route through the program.
摘要翻译：一种方法和相应的工具，所述方法包括：接收作为输入（a）表示通过可执行程序的控制流的更高级别的结构，所述较高级结构包括一个或多个级别的父节点，每个父节点表示内部结构包括一组一个或多个子节点和节点之间的一个或多个相关联的边缘; 和（b）至少一个开始和结束指令的指示。该方法还包括通过选择性地提取不同级别的父节点的节点来代表沿着该路线的不同区域来探测较高级结构的级别以提取表示通过程序从起始到结束指令的路由的子结构，依赖于开始和结束指令相对于父节点级别的位置; 并且基于所提取的子结构，估计通过程序的路线的执行时间。

3. 发明公开

US20230417896A1 MANIPULATION OF RADAR READINGS 审中-公开
公开(公告)号：US20230417896A1
公开(公告)日：2023-12-28
申请号：US18037153
申请日：2021-08-26
申请人： XMOS LTD
发明人： Hendrik Lambertus MULLER , Douglas Roger PULLEY
IPC分类号： G01S13/58 , G01S13/42 , G01S13/89
CPC分类号： G01S13/584 , G01S13/426 , G01S13/89
摘要： A system comprising: a radar sensor configured to produce a set of radar readings distributed amongst a plurality of distance bins; an image projection module configured to project at least some of the radar readings onto an image comprising a 2D Cartesian grid of pixels based on the respective azimuth angles and elevations, wherein for each pixel where a radar reading is present the pixel comprises a respective value of at least one non-binary channel comprising at least one of measured property of the radar reading; and a machine learning model for image recognition, arranged to receive the image and to detect an object therein, wherein the machine learning model is configured to perform the detection based on at the values of the at least one non-binary channel for each pixel.

4. 发明申请

US20210109760A1 PROCESSING SYSTEM 有权
公开(公告)号：US20210109760A1
公开(公告)日：2021-04-15
申请号：US16965074
申请日：2018-12-17
申请人： XMOS LTD
发明人： Henk Lambertus MULLER , Peter HEDINGER
IPC分类号： G06F9/38 , G06F9/30
摘要： A system comprising a data memory, a first processor with first execution pipeline, and a co-processor with second execution pipeline branching from the first pipeline via an inter-processor interface. The first pipeline can decode instructions from an instruction set comprising first and second instruction subsets. The first subset comprises a load instruction which loads data from the memory into a register file, and a compute instruction of a first type which performs a compute operation on such loaded data. The second subset includes a compute instruction of a second type which does not require a separate load instruction to first load data from memory into a register file, but instead reads data from the memory directly and performs a compute operation on that data, this reading being performed in a pipeline stage of the second pipeline that is aligned with the memory access stage of the first pipeline.

5. 发明授权

US08966488B2 Synchronising groups of threads with dedicated hardware logic 有权
标题翻译：使用专用硬件逻辑同步线程组
公开(公告)号：US08966488B2
公开(公告)日：2015-02-24
申请号：US11774219
申请日：2007-07-06
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009
摘要： The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.
摘要翻译：本发明提供了一种处理器，其包括被执行多个程序线程的执行单元，每个线程包括指令序列，以及用于同步线程的多个同步器。响应于执行单元执行一个或多个同步器关联指令，每个同步器可操作以与一组至少两个线程相关联。当这样关联时，每个同步器也可操作，以通过暂停该组中的线程的执行以等待该组的另一个线程中的同步点来同步该组的线程。

6. 发明授权

US08881117B2 Structural analyser 有权
标题翻译：结构分析仪
公开(公告)号：US08881117B2
公开(公告)日：2014-11-04
申请号：US12723489
申请日：2010-03-12
申请人： Andrew Stanford-Jason
发明人： Andrew Stanford-Jason
IPC分类号： G06F9/44 , G06F9/45 , G06F11/36
CPC分类号： G06F11/3604
摘要： A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.
摘要翻译：一种方法和相应的工具，所述方法包括：生成表示可执行程序的一部分的较低级控制流结构，所述下级控制流结构包括表示在程序内发生的操作的多个下级节点，以及多个方向边缘表示节点之间的节目流; 通过将多个下级节点和边缘匹配到表示内部结构的上级结构节点来产生更高级别的控制流结构，每个较高级结构节点表示一个或多个下级节点的组，一个或多个更多相关边缘; 并且使用所述较高级别的控制流结构来估计与处理器上的所述程序的执行相关的定时属性。高级结构节点仅由预定的一组结构节点模式选择，集合中的每个模式具有至多一个入口点和至多一个出口点。

7. 发明授权

US08843902B2 Program flow route constructor 有权
标题翻译：程序流程路径构造函数
公开(公告)号：US08843902B2
公开(公告)日：2014-09-23
申请号：US12723444
申请日：2010-03-12
申请人： Andrew Stanford-Jason
发明人： Andrew Stanford-Jason
IPC分类号： G06F9/45 , G06F11/36
CPC分类号： G06F11/3604
摘要： A method and corresponding tool for estimating program execution time. A higher-level structure is received as an input, representing control flow through an executable program. The higher-level structure comprises one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes. The levels of the higher-level structure are probed to extract a substructure representing a route through the program from a start instruction to an end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes. An execution time for the route through the program is estimated based on the extracted substructure, and a modification affecting the execution time is made in dependence on the estimation.
摘要翻译：一种用于估计程序执行时间的方法和相应的工具。接收到较高级别的结构作为输入，表示通过可执行程序的控制流程。较高级别的结构包括一个或多个级别的父节点，每个父节点表示内部结构，其包括一个或多个子节点的组以及节点之间的一个或多个相关联的边缘。通过选择性地提取不同级别的父节点的节点以根据位置沿着该路线来表示不同的区域，探测更高级别结构的级别以提取表示通过该程序的路由从起始指令到结束指令的子结构的开始和结束指令相对于父节点的级别。基于所提取的子结构来估计通过该程序的路线的执行时间，并且根据该估计进行影响执行时间的修改。

8. 发明授权

US08224884B2 Processor communication tokens 有权
标题翻译：处理器通信令牌
公开(公告)号：US08224884B2
公开(公告)日：2012-07-17
申请号：US12027435
申请日：2008-02-07
申请人： Michael David May
发明人： Michael David May
IPC分类号： G06F15/16
CPC分类号： G06F13/4291 , G06F15/17381
摘要： The invention provides a method of transmitting messages over an interconnect between processors, each message comprising a header token specifying a destination processor and at least one of a data token and a control token. The method comprises: executing a first instruction on a first one of the processors to generate a data token comprising a byte of data and at least one additional bit to identify that token as a data token, and outputting the data token from the first processor onto the interconnect as part of one of the messages. The method also comprises executing a second instruction on said first processor to generate a control token comprising a byte of control information and at least one additional bit to identify that token as a control token, and outputting the control token from the first processor onto the interconnect as part of one of the messages.
摘要翻译：本发明提供了一种在处理器之间的互连上发送消息的方法，每个消息包括指定目的地处理器的头标记和数据令牌和控制令牌中的至少一个。该方法包括：在第一个处理器上执行第一指令以产生包括数据字节和至少一个附加位的数据令牌，以将该令牌标识为数据令牌，并将数据令牌从第一处理器输出到互连作为其中一个消息的一部分。该方法还包括在所述第一处理器上执行第二指令以产生包括一个字节的控制信息的控制令牌和至少一个额外的比特，以将该令牌标识为控制令牌，以及将控制令牌从第一处理器输出到互连作为其中一个消息的一部分。

9. 发明授权

US11256516B2 Processing system with a main processor pipeline and a co-processor pipeline 有权
公开(公告)号：US11256516B2
公开(公告)日：2022-02-22
申请号：US16965074
申请日：2018-12-17
申请人： XMOS LTD
发明人： Henk Lambertus Muller , Peter Hedinger
IPC分类号： G06F9/38 , G06F9/30
摘要： A system comprising a data memory, a first processor with first execution pipeline, and a co-processor with second execution pipeline branching from the first pipeline via an inter-processor interface. The first pipeline can decode instructions from an instruction set comprising first and second instruction subsets. The first subset comprises a load instruction which loads data from the memory into a register file, and a compute instruction of a first type which performs a compute operation on such loaded data. The second subset includes a compute instruction of a second type which does not require a separate load instruction to first load data from memory into a register file, but instead reads data from the memory directly and performs a compute operation on that data, this reading being performed in a pipeline stage of the second pipeline that is aligned with the memory access stage of the first pipeline.

10. 发明授权

US07958333B2 Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected 有权
标题翻译：具有存储器访问级的处理器，其适于在没有检测到存储器访问操作时获取线程的指令
公开(公告)号：US07958333B2
公开(公告)日：2011-06-07
申请号：US11755119
申请日：2007-05-30
申请人： Michael David May
发明人： Michael David May
IPC分类号： G06F9/30 , G06F9/40 , G06F13/00 , G06F13/28 , G06F3/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
摘要翻译：用于执行线程的处理器和方法。处理器包括多个指令缓冲器，每个指令缓冲器用于缓冲相应的相关线程的指令，以及指令发布阶段，用于从指令缓冲器向存储器访问级发出指令。存储器访问级包括适于检测在每个发出的指令中是否定义存储器访问操作的逻辑，以及如果没有检测到存储器访问操作则获取另一指令。

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