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1. 发明授权

US08185722B2 Processor instruction set for controlling threads to respond to events 有权
标题翻译：处理器指令集，用于控制线程以响应事件
公开(公告)号：US08185722B2
公开(公告)日：2012-05-22
申请号：US11717616
申请日：2007-03-14
申请人： Michael David May
发明人： Michael David May
IPC分类号： G06F9/40
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4881 , Y02D10/24
摘要： The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread.
摘要翻译：本发明提供了一种包括执行单元和线程调度器的处理器，该线程调度器被配置为根据每个线程的相应状态来调度多个线程以供执行单元执行。所述执行单元被配置为执行管理所述状态的线程调度指令，所述线程调度指令至少包括：将状态设置为事件使能以允许线程接受事件的线程事件使能指令，设置状态暂停等待线程持续执行至少一个事件依赖，线程事件禁用指令将状态设置为事件禁用，以阻止线程接受事件。继续执行包括检索线程的连续点向量。

2. 发明申请

US20110066825A1 MESSAGE ROUTING SCHEME 有权
标题翻译：消息路由方案
公开(公告)号：US20110066825A1
公开(公告)日：2011-03-17
申请号：US12949690
申请日：2010-11-18
申请人： Michael David MAY
发明人： Michael David MAY
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/16
摘要： Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.
摘要翻译：节点阵列中的每个拥有者节点具有相应的本地节点地址，并且每个本地节点地址包括从大多数到最小有效的具有寻址意义的顺序的多个分量。每个节点包括：映射装置，被配置为将本地节点地址的每个组件映射到相应的路由方向;以及交换机，被配置为接收具有标识目的地节点的目的地节点地址的消息。交换机包括：用于将本地节点地址与目的地节点地址进行比较以识别最重要的非匹配分量的装置; 以及在映射到最重要的不匹配组件的方向上，在本地节点地址与目的地节点地址不匹配的情况下，将消息路由到另一节点的装置。

3. 发明申请

US20080301409A1 SCHEDULING THREADS IN A PROCESSOR 有权
标题翻译：在处理器中调度螺纹
公开(公告)号：US20080301409A1
公开(公告)日：2008-12-04
申请号：US11755119
申请日：2007-05-30
申请人： Michael David MAY
发明人： Michael David MAY
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： The invention provides a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of those instructions defining a memory access operation. The processor comprises: a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer; an instruction issue stage for issuing instructions from the instruction buffers; and a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage. The memory access stage comprises: detecting logic adapted to detect whether a memory access operation is defined in each issued instruction; and instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.
摘要翻译：本发明提供了一种用于执行线程的处理器，每个线程包括指令序列，所述指令定义操作，以及定义存储器访问操作的那些指令中的至少一些指令。处理器包括：多个指令缓冲器，每个指令缓冲器用于保持与该缓冲器相关联的线程的至少一个指令; 用于从指令缓冲器发出指令的指令发布阶段; 以及连接到存储器并被布置成接收由指令发布阶段发出的指令的存储器访问级。存储器访问级包括：检测逻辑，用于检测在每个发出的指令中是否定义存储器存取操作; 以及指令提取逻辑，其适于在没有检测到存储器访问操作时发起指令提取以获取线程的指令。

4. 发明申请

US20080263330A1 Clocked ports 有权
标题翻译：时钟端口
公开(公告)号：US20080263330A1
公开(公告)日：2008-10-23
申请号：US11785345
申请日：2007-04-17
申请人： Michael David May , Peter Hedinger , Alastair Dixon
发明人： Michael David May , Peter Hedinger , Alastair Dixon
IPC分类号： G06F9/30
CPC分类号： G06F13/385 , G06F9/30032 , G06F9/3009 , G06F9/3851 , G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.
摘要翻译：处理器具有接口部分和内部环境。接口部分包括至少一个端口。内部环境包括执行单元，其执行依赖于第一定时信号的指令，并根据第一定时信号在内部部分和至少一个端口之间传送数据; 以及线程调度器，用于调度由所述执行单元执行的多个线程，每个线程包括指令序列，并且所述线程调度器被配置为根据所述第一定时信号调度所述线程。端口被配置为根据第二定时信号在端口和外部环境之间传送数据，并且根据第二定时信号来改变就绪信号，以指示与外部环境的数据传输。线程调度器被配置为根据就绪信号调度一个或多个相关联的线程以执行。

5. 发明申请

US20080229083A1 Processor instruction set 有权
标题翻译：处理器指令集
公开(公告)号：US20080229083A1
公开(公告)日：2008-09-18
申请号：US11717616
申请日：2007-03-14
申请人： Michael David May
发明人： Michael David May
IPC分类号： G06F7/38
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4881 , Y02D10/24
摘要： The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread.
摘要翻译：本发明提供了一种包括执行单元和线程调度器的处理器，该线程调度器被配置为根据每个线程的相应状态来调度多个线程以供执行单元执行。所述执行单元被配置为执行管理所述状态的线程调度指令，所述线程调度指令至少包括：将状态设置为事件使能以允许线程接受事件的线程事件使能指令，设置状态暂停等待线程持续执行至少一个事件依赖，线程事件禁用指令将状态设置为事件禁用，以阻止线程接受事件。继续执行包括检索线程的连续点向量。

6. 发明申请

US20080229059A1 Message routing scheme 有权
标题翻译：消息路由方案
公开(公告)号：US20080229059A1
公开(公告)日：2008-09-18
申请号：US11717621
申请日：2007-03-14
申请人： Michael David May
发明人： Michael David May
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.
摘要翻译：节点阵列中的每个拥有者节点具有相应的本地节点地址，并且每个本地节点地址包括从大多数到最小有效的具有寻址意义的顺序的多个分量。每个节点包括：映射装置，被配置为将本地节点地址的每个组件映射到相应的路由方向;以及交换机，被配置为接收具有标识目的地节点的目的地节点地址的消息。交换机包括：用于将本地节点地址与目的地节点地址进行比较以识别最重要的非匹配分量的装置; 以及在映射到最重要的不匹配组件的方向上，在本地节点地址与目的地节点地址不匹配的情况下，将消息路由到另一节点的装置。

7. 发明授权

US06658514B1 Interrupt and control packets for a microcomputer 有权
标题翻译：中断和控制微计算机的数据包
公开(公告)号：US06658514B1
公开(公告)日：2003-12-02
申请号：US09301651
申请日：1999-04-28
申请人： Andrew Michael Jones , Michael David May
发明人： Andrew Michael Jones , Michael David May
IPC分类号： G06F1340
CPC分类号： G06F13/385
摘要： A computer system comprises on-chip a CPU with at least one different module, both having circuitry to generate two types of address request packets, one being a control command packet to which a destination device must respond on receipt and the other type being an interrupt request with a priority indicator for a selective response by the destination device.
摘要翻译：计算机系统包括具有至少一个不同模块的CPU的片上，两者具有生成两种类型的地址请求分组的电路，一个是目的地设备在接收时必须响应的控制命令分组，另一种类型是中断请求具有目标设备的选择性响应的优先级指示符。

8. 发明授权

US06356960B1 Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port 有权
标题翻译：具有片上CPU的微处理器响应于通过调试端口接收到的控制信号从外部调试设备中的存储器获取调试例程
公开(公告)号：US06356960B1
公开(公告)日：2002-03-12
申请号：US09710775
申请日：2000-11-09
申请人： Andrew Michael Jones , David Alan Edwards , Michael David May
发明人： Andrew Michael Jones , David Alan Edwards , Michael David May
IPC分类号： G06F1314
CPC分类号： G06F11/3656
摘要： There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.
摘要翻译：公开了一种包括在集成电路芯片上的微处理器的计算机系统，该集成电路芯片包括片上CPU和连接到集成电路上的通信总线的调试端口以及外部调试计算机设备。外部调试装置可操作以通过调试端口发送控制信号：a）停止CPU执行从第一片上存储器获得的指令; b）从与外部调试计算机设备相关联的第二存储器提供要由CPU执行的调试例程; 以及c）在从由外部调试装置确定的地址执行指令的例程之后重新启动CPU的操作。片上CPU可操作于独立于调试例程的第一存储器中的代码。还公开了一种使用外部调试装置操作这种计算机系统的方法。

9. 发明授权

US6009508A System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis 失效
标题翻译：用于在基于FIFO的多值存储器中用单个地址寻址多个数据值的系统和方法
公开(公告)号：US6009508A
公开(公告)日：1999-12-28
申请号：US938242
申请日：1997-09-26
申请人： Michael David May , Andrew Craig Sturges , Nathan Mackenzie Sidwell
发明人： Michael David May , Andrew Craig Sturges , Nathan Mackenzie Sidwell
IPC分类号： G06F9/30 , G06F13/00
CPC分类号： G06F9/30167 , G06F9/30149 , G06F9/30163 , G06F9/30178 , G06F9/3816
摘要： A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations.A method of executing a succession of instructions in a computer system is also described.
摘要翻译：计算机系统具有相对于在指令执行期间可能保持的数据项的数量减少地址位数的指令。指令集包括可选择的指令，多个指令各自包括标识要通过执行指令执行的操作的一组比特位置和第二组比特位置，以识别数据存储位置的地址，以用于执行指令。计算机系统还包括多个可寻址数据存储位置，用于在执行指令序列期间同时保持多个数据值，其中至少一个数据存储位置包括要求指令中的单个地址的多值存储并且被安排成以先入先出的方式同时保存多个数据值。因此，这增加了可以相对于可由第二组位位置识别的地址数量来保持的数据值的数量。还描述了在计算机系统中执行一系列指令的方法。

10. 发明申请

US20110131396A1 TIMING ANALYSIS 审中-公开
标题翻译：时序分析
公开(公告)号：US20110131396A1
公开(公告)日：2011-06-02
申请号：US12628706
申请日：2009-12-01
申请人： Michael David May , Hendrik Lambertus Muller
发明人： Michael David May , Hendrik Lambertus Muller
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F11/0757
摘要： One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to identify an opcode representing a trap-if-late instruction in said sequence, and in response to execute the trap-if-late instruction by comparing a target value to the counter value and generating an exception on condition that the counter value represents a time that is late relative to said target value. Another aspect provides a compiler for inserting trap-if-late instructions based on timing constraints in higher-level code.
摘要翻译：本发明的一个方面提供了一种处理器，包括：执行单元，被配置为执行每个包括相应操作码的指令序列; 以及耦合到执行单元并被布置成在执行期间生成周期性更新的计数器值的计数器。执行单元包括逻辑，其被配置为识别表示所述序列中的陷阱 - 如果 - 延迟的指令的操作码，并且响应于通过将目标值与计数器值进行比较来执行陷阱 - 如果 - 延迟的指令，并且在计数器值表示相对于所述目标值较晚的时间。另一方面提供了一种编译器，用于根据较高级代码中的时序约束插入陷阱即时延迟指令。

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