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1. 发明申请

US20180172764A1 METHOD, SYSTEM AND APPARATUS FOR TUNING AN INTEGRATED EMBEDDED SUBSYSTEM 审中-公开
公开(公告)号：US20180172764A1
公开(公告)日：2018-06-21
申请号：US15385971
申请日：2016-12-21
申请人： ARM Limited
发明人： Daniel Lewis CROSS , Brian Alan NAGEL
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3167 , G01R31/31724 , G01R31/31908
摘要： A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (DUT) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the DUT, test firmware of the invoked tests is loaded into the target embedded subsystem. The target embedded subsystem executes the tests under control of the tester in accordance with test parameters received from the tester over the command channel and in accordance with test commands received from the tester over a test signaling channel. The target embedded subsystem returns results of the one or more tests to the tester via the command channel. The results can be used to trim analog characteristics of the target embedded subsystem and can be stored in memory. The test firmware can then be deleted to free up memory space.

2. 发明授权

US09980070B2 Apparatus and method for measuring relative frequency response of audio device microphones 有权
公开(公告)号：US09980070B2
公开(公告)日：2018-05-22
申请号：US15593170
申请日：2017-05-11
申请人： Cirrus Logic, Inc.
发明人： Samuel Ponvarma Ebenezer , Seth Suppappola , Clifton Cordes
IPC分类号： H04R29/00 , H04R1/08 , H04R1/32 , H04R3/00 , G01R31/3167 , G01R31/319 , G01R31/317 , G01R25/00
CPC分类号： H04R29/006 , G01R25/00 , G01R31/3167 , G01R31/31701 , G01R31/31901 , G01R31/31905 , H04R1/083 , H04R1/326 , H04R3/005 , H04R29/004 , H04R29/005
摘要： Test apparatus measuring relative frequency response of first and second microphones includes a rotatable carrier. First and second microphones are sealingly clamped against a mounting surface of the carrier aligned with first and second apertures therein, such apertures lying equidistant from, and on opposite sides of, the carrier's axis of rotation. The carrier initially positions the first microphone closest to an audible signal source, and the responses of the microphones to an audible excitation signal are measured. The carrier is rotated 180 degrees, and the measurements are repeated. Elongated strips of gasket material are used to align the microphones and to form a seal with the carrier. When microphones are mounted deep within an audio device, the audio device is sealingly clamped against a mounting plate, sequentially aligning the mounting plate aperture with first and second apertures of the audio device housing corresponding to first and second microphones disposed therein.

3. 发明申请

US20180003770A1 Mixed-Signal Integrated Circuit 审中-公开
公开(公告)号：US20180003770A1
公开(公告)日：2018-01-04
申请号：US15705558
申请日：2017-09-15
申请人： Huawei Technologies Co., Ltd.
发明人： Udi Nir , Zhaocai Lin , Tingting Li
IPC分类号： G01R31/3185 , H03K19/003
CPC分类号： G01R31/318536 , G01R31/3167 , G01R31/318583 , G06F17/5022 , H03K19/003 , H03K19/17748
摘要： A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

4. 发明申请

US20170242419A1 DUT CONTINUITY TEST WITH ONLY DIGITAL IO STRUCTURES APPARATUS AND METHODS ASSOCIATED THEREOF 审中-公开
公开(公告)号：US20170242419A1
公开(公告)日：2017-08-24
申请号：US15593621
申请日：2017-05-12
申请人： The United States of America as represented by the Secretary of the Navy
发明人： Adam Duncan , Matthew Gadlage
IPC分类号： G05B19/042 , G06F13/38 , G01R31/3167 , G01R31/02
CPC分类号： G05B19/0423 , G01R31/024 , G01R31/11 , G01R31/3167 , G05B2219/21114 , G06F13/385
摘要： A method and system for determining short, open, and good connections using digital input and output (TO) structures in a device under test (DUT) continuity test, through the combined methods of using resistance-capacitance (RC) delay, time domain reflectometry (TDR), and forcing voltage on to a single IO pin of the DUT while measuring voltage on remaining IO pins of said DUT. In one embodiment, the combined methods are executed without the DUT in a test socket to produce a first set of test values and also with the DUT in a test socket to produce a second set of test values. The first and second sets of test values are compared to determine if one or more circuits of the DUT have a short circuit, an open circuit, or are a good (have an electrical connection that is not a short circuit or an open circuit) circuit.

5. 发明授权

US09354266B2 Universal jitter meter and phase noise measurement 有权
标题翻译：通用抖动计和相位噪声测量
公开(公告)号：US09354266B2
公开(公告)日：2016-05-31
申请号：US13491210
申请日：2012-06-07
申请人： Mihai A. Sanduleanu
发明人： Mihai A. Sanduleanu
IPC分类号： G01R29/26 , G01R31/00 , G01R31/26 , G01R31/317 , G01R31/3167 , G01R31/333
CPC分类号： G01R29/26 , G01R31/001 , G01R31/2646 , G01R31/3167 , G01R31/31709 , G01R31/333
摘要： A device and method for measuring jitter includes a capacitive element capable of being selectively charged, wherein the selection is made by a received signal from which an accumulated jitter value is to be determined. An analog-to-digital converter is coupled to the capacitive element to determine a voltage across the capacitive element after a number of cycles of the received signal. A determination module is coupled to the analog-to-digital converter to output the accumulated jitter value of the received signal using the voltage, wherein the accumulated jitter value is accumulated over the number of cycles.
摘要翻译：用于测量抖动的装置和方法包括能够被选择性地充电的电容元件，其中通过接收信号进行选择，从该信号中确定累加的抖动值。模数转换器耦合到电容元件，以在接收信号的多个周期之后确定电容元件两端的电压。确定模块耦合到模数转换器，以使用电压输出接收信号的累积抖动值，其中累积的抖动值在周期数上累积。

6. 发明授权

US09322878B2 Semiconductor device, physical quantity sensor, electronic apparatus, and moving object 有权
标题翻译：半导体器件，物理量传感器，电子设备和移动物体
公开(公告)号：US09322878B2
公开(公告)日：2016-04-26
申请号：US14227253
申请日：2014-03-27
申请人： Seiko Epson Corporation
发明人： Hideki Sato
IPC分类号： G01R31/3185 , G01R31/3167
CPC分类号： G01R31/3177 , G01R31/3167 , G01R31/31701 , G01R31/318536 , G01R31/318541 , G01R31/318558
摘要： A semiconductor device includes a digital circuit having a scan test mode. The digital circuit includes a first flip-flop forming a part of a scan chain when in the scan test mode, and a first selector provided on an input side of the first flip-flop. The first selector is capable of selecting a first signal when not in the scan test mode, and selecting a second signal that is different from the first signal when in the scan test mode.
摘要翻译：半导体器件包括具有扫描测试模式的数字电路。数字电路包括在扫描测试模式下形成扫描链的一部分的第一触发器，以及设置在第一触发器的输入侧的第一选择器。第一选择器能够在不处于扫描测试模式时选择第一信号，并且在扫描测试模式中选择与第一信号不同的第二信号。

7. 发明授权

US09239358B2 Optimized automated test equipment multi-path receiver concept 有权
标题翻译：优化的自动化测试设备多路径接收机概念
公开(公告)号：US09239358B2
公开(公告)日：2016-01-19
申请号：US13391260
申请日：2009-08-18
申请人： Kyle David Holzer
发明人： Kyle David Holzer
IPC分类号： H04B17/00 , G01R31/3167 , G01R31/319
CPC分类号： G01R31/3167 , G01R31/31926
摘要： A multi-path receiver for automated test equipment. The multi-path receiver includes an input for receiving low-power signals and high-power signals. The high-power signals have signal amplitude higher than the low-power signals. The multi-path receiver further comprises an output for outputting a received signal, a first path for transmitting a received high-power signal from the input to the output and a second path for transmitting a received low-power signal from the input to the output. The second path comprises an amplifier. A first switch is provided for switching a received high-power signal to the first path and for switching a received low-power signal to the second path. A high-power amplifier is also connected between the input and the first switch for amplifying the received signal independent of its input power before it is switched with the first path or the second path.
摘要翻译：用于自动测试设备的多路径接收器。多路径接收机包括用于接收低功率信号和高功率信号的输入。高功率信号的信号幅度高于低功率信号。多路径接收机还包括用于输出接收信号的输出端，用于从接收到输出的接收信号发送接收到的高功率信号的第一路径和用于将接收到的低功率信号从输入发送到输出端的第二路径。第二路径包括放大器。提供第一开关用于将接收到的高功率信号切换到第一路径并将接收到的低功率信号切换到第二路径。高功率放大器也连接在输入端和第一开关之间，用于在与第一路径或第二路径切换之前独立于其输入功率放大接收信号。

8. 发明授权

US09194884B1 Integrated circuit with analog device fault detection 有权
标题翻译：具有模拟器件故障检测的集成电路
公开(公告)号：US09194884B1
公开(公告)日：2015-11-24
申请号：US13597163
申请日：2012-08-28
申请人： John Archie Mossman , Robert A. McCarthy
发明人： John Archie Mossman , Robert A. McCarthy
IPC分类号： G01R31/3187 , G01R1/00
CPC分类号： G01R31/02 , G01R1/00 , G01R31/3167 , G01R31/3187 , H01H1/00 , H01L21/00 , H02J1/00 , H03F1/52 , H03F3/45076
摘要： An integrated circuit with analog device fault detection includes an integrated circuit die having an analog device, an on-line fault detector and a control circuit. The analog device has a power input, an analog device input and an analog device output and the on-line fault detector is coupled to at least one of the power input, the analog device input and the analog device output and has a fault detector output. The control circuit is coupled to the fault detector and responsive to the fault detector output. Detector self-test (DST) circuitry can be provided to test the on-line fault detector and one or more circuit breakers can be provided to protect the analog device and other devices attached to the analog device.
摘要翻译：具有模拟设备故障检测的集成电路包括具有模拟设备的集成电路管芯，在线故障检测器和控制电路。模拟设备具有电源输入，模拟设备输入和模拟设备输出，并且在线故障检测器耦合到电源输入，模拟设备输入和模拟设备输出中的至少一个，并且具有故障检测器输出。控制电路耦合到故障检测器并响应于故障检测器的输出。可以提供检测器自检（DST）电路来测试在线故障检测器，并且可以提供一个或多个断路器来保护模拟设备和连接到模拟设备的其他设备。

9. 发明申请

US20140298127A1 SEMICONDUCTOR DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC APPARATUS, AND MOVING OBJECT 有权
标题翻译：半导体器件，物理量传感器，电子设备和移动对象
公开(公告)号：US20140298127A1
公开(公告)日：2014-10-02
申请号：US14227253
申请日：2014-03-27
申请人： SEIKO EPSON CORPORATION
发明人： Hideki Sato
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/3167 , G01R31/31701 , G01R31/318536 , G01R31/318541 , G01R31/318558
摘要： A semiconductor device includes a digital circuit having a scan test mode. The digital circuit includes a first flip-flop forming a part of a scan chain when in the scan test mode, and a first selector provided on an input side of the first flip-flop. The first selector is capable of selecting a first signal when not in the scan test mode, and selecting a second signal that is different from the first signal when in the scan test mode.
摘要翻译：半导体器件包括具有扫描测试模式的数字电路。数字电路包括在扫描测试模式下形成扫描链的一部分的第一触发器，以及设置在第一触发器的输入侧的第一选择器。第一选择器能够在不处于扫描测试模式时选择第一信号，并且在扫描测试模式中选择与第一信号不同的第二信号。

10. 发明申请

US20130179759A1 INCREMENTAL MODIFICATION OF AN ERROR DETECTION CODE BACKGROUND OF THE INVENTION 有权
标题翻译：错误检测码的增量修改背景技术
公开(公告)号：US20130179759A1
公开(公告)日：2013-07-11
申请号：US13348453
申请日：2012-01-11
申请人： Lior ARONOVICH , Michael HIRSCH , Shmuel Thomas Klein , Yair TOAFF
发明人： Lior ARONOVICH , Michael HIRSCH , Shmuel Thomas Klein , Yair TOAFF
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G01R31/3167 , G06F11/1004 , H03M13/093
摘要： Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.
摘要翻译：提供了用于错误检测码操作的增量修改的示例性方法，系统和计算机程序产品实施例。在一个实施例中，仅作为示例，对于需要计算和验证第一错误检测码（EDC）值的数据块，并且对于在独立时间变得可用和修改的至少一个随机定位的子块正在进行修改间隔，为每个随机定位的子块计算第二EDC值。应用第二EDC值的增量效应来计算第一EDC值，并且在替换随机定位的子块中的至少一个时重新计算第一EDC值。资源消耗与添加和修改的随机定位的子块中的至少一个的大小成比例。公开了附加的系统和计算机程序产品实施例并提供相关的优点。

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