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1. 发明公开

US20240175920A1 BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING THE SAME 审中-公开
公开(公告)号：US20240175920A1
公开(公告)日：2024-05-30
申请号：US18433456
申请日：2024-02-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： CHU-FENG LIAO , HUNG-PING CHENG , YUAN-YAO CHANG , SHUO-WEN CHANG
IPC分类号： G01R31/317 , H01L21/66
CPC分类号： G01R31/31722 , G01R31/31723 , G01R31/31724 , G01R31/31725 , H01L22/34
摘要： The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.

2. 发明公开

US20240142520A1 INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMS 审中-公开
公开(公告)号：US20240142520A1
公开(公告)日：2024-05-02
申请号：US18049775
申请日：2022-10-26
申请人： NXP USA, Inc.
发明人： Alexander Hoefler , Jeffrey Stump
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/318541 , G01R31/31722
摘要： A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.

3. 发明授权

US11835578B2 Selectable JTAG or trace access with data store and output 有权
公开(公告)号：US11835578B2
公开(公告)日：2023-12-05
申请号：US17579629
申请日：2022-01-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/317 , G06F11/27 , G01R31/3185 , G01R31/3177 , G06F11/267 , G06F11/26 , G06F11/34
CPC分类号： G01R31/31723 , G01R31/3177 , G01R31/31722 , G01R31/31725 , G01R31/31727 , G01R31/318572 , G06F11/267 , G06F11/27 , G06F11/261 , G06F11/3466
摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

4. 发明授权

US11835577B2 Method for allocating addresses and corresponding units 有权
公开(公告)号：US11835577B2
公开(公告)日：2023-12-05
申请号：US17422701
申请日：2019-01-15
申请人： Christoph Heldeis
发明人： Christoph Heldeis
IPC分类号： G01R31/317 , G01R31/3185 , G06F13/37
CPC分类号： G01R31/31722 , G01R31/31853 , G01R31/318536 , G06F13/37
摘要： A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

5. 发明授权

US11668748B2 Addressable test chip 有权
公开(公告)号：US11668748B2
公开(公告)日：2023-06-06
申请号：US17648935
申请日：2022-01-25
申请人： SEMITRONIX CORPORATION
发明人： Fan Lan , Weiwei Pan , Shenzhi Yang , Yongjun Zheng
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31722 , G01R31/2882 , G01R31/2886
摘要： A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

6. 发明申请

US20190235022A1 ADDRESSABLE TEST CHIP WITH SENSING CIRCUIT 审中-公开
公开(公告)号：US20190235022A1
公开(公告)日：2019-08-01
申请号：US16377471
申请日：2019-04-08
申请人： Semitronix Corporation
发明人： Fan LAN
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31722 , G01R31/2882 , G01R31/2886
摘要： An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.

7. 发明申请

US20180188324A1 ADDRESSABLE TEST CHIP TEST SYSTEM 审中-公开
公开(公告)号：US20180188324A1
公开(公告)日：2018-07-05
申请号：US15859306
申请日：2017-12-29
申请人： Semitronix Corporation
发明人： Fan LAN , Shenzhi YANG , YONGJUN ZHENG , WEIWEI PAN
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31722 , G01R31/2882 , G01R31/2886
摘要： To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

8. 发明申请

US20170176523A1 INTERFACES FOR WIRELESS DEBUGGING 有权
公开(公告)号：US20170176523A1
公开(公告)日：2017-06-22
申请号：US14975685
申请日：2015-12-18
申请人： Intel Corporation
发明人： Sankaran M. Menon , Bradley H. Smith , Jinshi Huang , Rolf H. Kuehnis
IPC分类号： G01R31/3177 , G01R31/317 , H04W4/00
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31705 , G01R31/31722 , H04W4/80
摘要： Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.

9. 发明申请

US20160047860A1 REDUCED SIGNALING INTERFACE METHOD & APPARATUS 审中-公开
公开(公告)号：US20160047860A1
公开(公告)日：2016-02-18
申请号：US14925536
申请日：2015-10-28
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

10. 发明授权

US09217773B2 Addressable tap selection aux i/o, linking, address, instruction, control circuitry 有权
标题翻译：可寻址抽头选择辅助i / o，链接，地址，指令，控制电路
公开(公告)号：US09217773B2
公开(公告)日：2015-12-22
申请号：US14567299
申请日：2014-12-11
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。在本公开的第五方面中，一种接口选择电路，图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

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