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1. 发明授权

US11921160B2 Using scan chains to read out data from integrated sensors during scan tests 有权
公开(公告)号：US11921160B2
公开(公告)日：2024-03-05
申请号：US17834433
申请日：2022-06-07
申请人： Synopsys, Inc.
发明人： Bartosz Grzegorz Gajda , Anubhav Sinha
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318547 , G01R31/318552 , G01R31/318566 , G01R31/318569 , G01R31/31858
摘要： Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

2. 发明授权

US11879942B1 Core and interface scan testing architecture and methodology 有权
公开(公告)号：US11879942B1
公开(公告)日：2024-01-23
申请号：US17823670
申请日：2022-08-31
申请人： Micron Technology, Inc.
发明人： Banadappa Shivaray , Shrikrishna Pundoor , Mahesh Rawal , Aviral Agarwal
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/31855 , G01R31/31858 , G01R31/318525 , G01R31/318563 , G01R31/318566
摘要： Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.

3. 发明授权

US11852685B2 Stimulated circuits and fault testing methods 有权
公开(公告)号：US11852685B2
公开(公告)日：2023-12-26
申请号：US17571033
申请日：2022-01-07
申请人： Hamilton Sundstrand Corporation
发明人： Christopher Blazer , Brian Ross
IPC分类号： G01R31/319 , G01R31/3185
CPC分类号： G01R31/31926 , G01R31/318566 , G01R31/318572
摘要： A logic gate system for fault insertion testing can include a logic gate module having a plurality of input pins. The plurality of input pins can include an input signal pin configured to receive an input signal, a power supply input pin configured to receive power from a power supply, and a test input pin. The logic gate module can also include an output pin connected to the input pins via one or more logic gates. The logic gate system can include a power supply line connected to the power supply input pin and the test input pin. The logic gate system can also include a zero-ohm jumper resistor disposed between the power supply input pin and the test input pin. The zero-ohm resistor can be configured to be replaced with a low ohm resistor to allow reverse driving a voltage on the test input pin. The one or more logic gates can be configured to reverse an output at the output pin when the voltage on the test input pin is reverse driven.

4. 发明授权

US09727399B1 Residue-based checking of a shift operation 有权
公开(公告)号：US09727399B1
公开(公告)日：2017-08-08
申请号：US15279752
申请日：2016-09-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Steven R. Carlough , Petra Leber , Silvia M. Mueller , Andreas Wagner
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0751 , G01R31/318566 , G06F7/00 , G06F11/0736 , G06F11/079 , G06F11/22
摘要： A residue-based error checking mechanism is provided for checking for error in a shift operation of a shifter. The checking includes: partitioning an input vector into the shifter into one or more bit groups of bit width W; generating a predicted residue on the input vector being shifted, the generating including masking out any bit group of bit width W fully shifted out by the shift operation from contributing to the predicted residue, and the generating accounting for any bits of a bit group of the input vector partially shifted out by the shift operation; generating a result residue on a result vector of the shift operation; and comparing the result residue with the predicted residue to check for an error in the result vector of the shift operation.

5. 发明申请

US20170059651A1 IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST 有权
标题翻译：识别电路故障的扫描测试电池的故障
公开(公告)号：US20170059651A1
公开(公告)日：2017-03-02
申请号：US14835650
申请日：2015-08-25
申请人： Synopsys, Inc.
发明人： Subhadip Kundu , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/318566 , G01R31/318547
摘要： A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.
摘要翻译：所公开的配置用于识别至少一个故障指示被测电路CUT的扫描测试单元，具有多个扫描测试单元的CUT。该配置包括通过CUT的压缩器生成多个错误签名，其中多个错误签名的每个错误签名由包括至少一个故障指示位的相应的位序列组成，将每个错误签名分配给至少第一，第二和第三签名类型，根据指示相应错误签名的比特的故障总数，并将至少预定义的最小数量的错误签名映射到多个扫描测试单元中的各个扫描测试单元。对于每个错误签名，映射的优先级由相应错误签名已被分配给的签名类型来确定。

6. 发明授权

US09519026B2 Compressed scan testing techniques 有权
标题翻译：压缩扫描测试技术
公开(公告)号：US09519026B2
公开(公告)日：2016-12-13
申请号：US14502284
申请日：2014-09-30
申请人： Apple Inc.
发明人： Bibo Li , Andrew J. Copperhall , Bo Yang
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318566 , G01R31/318544
摘要： Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.
摘要翻译：公开了与测试设备有关的技术。在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。在该实施例中，第一测试基于第一压缩测试图案。在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。在该实施例中，多个压缩测试模式指定一对一模式。在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

7. 发明申请

US20160359377A1 TECHNIQUES FOR REDUCING MESSAGING REQUIREMENTS IN WIRELESS POWER DELIVERY ENVIRONMENTS 审中-公开
标题翻译：在无线电力输送环境中减少呼叫要求的技术
公开(公告)号：US20160359377A1
公开(公告)日：2016-12-08
申请号：US15176608
申请日：2016-06-08
申请人： Ossia Inc.
发明人： Hatem Zeine , Dale Mayes , Fady El-Rukby
IPC分类号： H02J50/20 , H04W4/12 , H04W8/00 , H02J7/02 , H02J50/80
CPC分类号： H02J50/80 , G01R31/318566 , G01R31/40 , H02J7/0004 , H02J7/025 , H02J7/045 , H02J50/20 , H02J50/40 , H04L12/2818 , H04L12/6418 , H04L67/12 , H04L2012/2841 , H04W4/12 , H04W8/005 , H04W52/0212 , Y04S40/18
摘要： Techniques are described for retention of known data within a wireless power transmission system, or within a cloud-based processing system. In order to perform scheduling procedures for determining which device to power, it is necessary to collect data regarding a device, e.g., the battery type, power usage, device model, present charge level and amount of power delivered per power cycle. A wireless power receiver client typically needs to collect or infer the information from the device and then provide the information directly to the charger via a messaging protocol. In existing wireless power transmission systems, information is re-transmitted to the wireless power transmission system every time the receiver engages or reengages the system.
摘要翻译：描述了在无线电力传输系统内或在基于云的处理系统内保留已知数据的技术。为了执行用于确定哪个设备供电的调度过程，有必要收集关于设备的数据，例如电池类型，功率使用，设备模型，当前充电水平以及每个功率周期传送的功率量。无线电力接收机客户端通常需要从设备收集或推断信息，然后通过消息协议将信息直接提供给充电器。在现有的无线电力传输系统中，每当接收机接合或重新接入系统时，将信息重新发送到无线电力传输系统。

8. 发明申请

US20160274184A1 SEMICONDUCTOR APPARATUS AND DESIGN APPARATUS 审中-公开
标题翻译：半导体设备和设计设备
公开(公告)号：US20160274184A1
公开(公告)日：2016-09-22
申请号：US14964362
申请日：2015-12-09
申请人： Renesas Electronics Corporation
发明人： Hiroyuki IWATA
IPC分类号： G01R31/3177 , G06F17/50
CPC分类号： G06F17/5045 , G01R31/318563 , G01R31/318566
摘要： In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.
摘要翻译：在压缩扫描中，测试步骤的数量减少，而不会降低缺陷效率。半导体装置包括一个或多个扫描链，每个扫描链包括串联连接的一个或多个MMSFF和组合电路，并且可以在扫描移位操作和捕获操作之间切换。 MMSFF包括选择外部输入的外部输入测试信号和在同一扫描链中的前一级经由MMSFF输入的移位测试信号的MUX，以及输出外部输入测试之一的FF 信号和由MUX选择的移位测试信号。

9. 发明授权

US09448282B1 System and method for bit-wise selective masking of scan vectors for X-value tolerant built-in self test 有权
标题翻译：用于X值容忍内置自检的扫描向量的逐位选择性屏蔽的系统和方法
公开(公告)号：US09448282B1
公开(公告)日：2016-09-20
申请号：US14179299
申请日：2014-02-12
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： Dale Edward Meehl
IPC分类号： G01R31/3185 , G01R31/3177 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/318335 , G01R31/31703 , G01R31/318536 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.
摘要翻译：提供了一种系统和方法，用于在内置自检（BIST）期间在集成电路（IC）的扫描通道中对X值进行选择性逐位屏蔽。根据在IC的仿真中识别的X值的位置选择性地生成复合掩模图案。复合掩模图案被存储在IC上并在被应用于IC的操作扫描结果的同时循环地保持。复合掩模图案在多个扫描迭代中被再循环，以有效地防止X值影响表示IC的功能指纹的BIST的结果签名，并且最小化复合掩模图案的存储要求。

10. 发明授权

US09250287B2 On-chip comparison and response collection tools and techniques 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US09250287B2
公开(公告)日：2016-02-02
申请号：US14570731
申请日：2014-12-15
申请人： Mentor Graphics Corporation
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

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