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1. 发明申请

US20180196103A1 TEST ARCHITECTURE WITH AN FPGA BASED TEST BOARD TO SIMULATE A DUT OR END-POINT 审中-公开
公开(公告)号：US20180196103A1
公开(公告)日：2018-07-12
申请号：US15914553
申请日：2018-03-07
申请人： Advantest Corporation
发明人： Duane CHAMPOUX , Mei-Mei SU
IPC分类号： G01R31/317
CPC分类号： G01R31/31724 , G01R31/2601 , G01R31/31723 , G01R31/31903 , G01R31/31907 , G01R31/31908 , G01R31/31919 , G01R35/00 , G06F11/263
摘要： An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

2. 发明授权

US09739832B2 Test messaging demodulate and modulate on separate power pads 有权
公开(公告)号：US09739832B2
公开(公告)日：2017-08-22
申请号：US15205527
申请日：2016-07-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/317 , G01R31/319 , G01R31/28 , G01R31/3177
CPC分类号： G01R31/31723 , G01R31/2851 , G01R31/2884 , G01R31/31721 , G01R31/3177 , G01R31/31917 , G01R31/31919
摘要： The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

3. 发明授权

US09411011B2 Test messaging demodulate and modulate on separate power pads 有权
标题翻译：测试消息在单独的电源板上解调和调制
公开(公告)号：US09411011B2
公开(公告)日：2016-08-09
申请号：US14599849
申请日：2015-01-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/319
CPC分类号： G01R31/31723 , G01R31/2851 , G01R31/2884 , G01R31/31721 , G01R31/3177 , G01R31/31917 , G01R31/31919
摘要： The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
摘要翻译：本公开描述了一种用于将设备的电源和接地终端用作设备的测试和/或调试接口的新颖方法和装置。根据本公开，通过施加到设备的电源端子的DC电压来调制消息，以向设备输入测试/调试消息并从设备输出测试/调试消息。本公开有利地允许在没有任何共享或专用测试或调试接口终端的设备的情况下测试和/或调试设备。

4. 发明授权

US09140752B2 Tester hardware 有权
标题翻译：测试仪硬件
公开(公告)号：US09140752B2
公开(公告)日：2015-09-22
申请号：US13908876
申请日：2013-06-03
申请人： ADVANTEST CORPORATION
发明人： Hiromi Oshima
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3183 , G11C29/56 , G01R31/319
CPC分类号： G01R31/3177 , G01R31/318371 , G01R31/31919 , G01R31/31924 , G11C29/56004
摘要： A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware.
摘要翻译：服务器存储多个配置数据。测试器硬件被配置为能够根据存储在可重写非易失性存储器中的配置数据来改变其功能的至少一部分，以向DUT提供电源电压，以将信号发送到DUT，并且接收信号从DUT。配置信息技术设备，使得（i）当测试系统建立时，信息技术设备根据用户的输入从服务器获取配置数据，并将配置数据写入非易失性存储器。此外，信息技术设备被配置为使得（ii）当DUT被测试时，信息技术设备执行测试程序，以便控制测试仪硬件，并处理由测试仪硬件获取的数据。

5. 发明授权

US08941400B2 Parallel scan paths with three bond pads, distributors and collectors 有权
标题翻译：具有三个焊盘，分配器和收集器的并行扫描路径
公开(公告)号：US08941400B2
公开(公告)日：2015-01-27
申请号：US14268073
申请日：2014-05-02
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3187 , G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.
摘要翻译：具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。这使得更长的并行扫描路径能够连接到功能电路。扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。扫描分配器和集电极电路可以形成在核心电路（704）中。然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

6. 发明申请

US20140229782A1 Automatic Test Equipment 审中-公开
标题翻译：自动测试设备
公开(公告)号：US20140229782A1
公开(公告)日：2014-08-14
申请号：US14259043
申请日：2014-04-22
申请人： Jochen Rueter , Simone Rehm , Joerg-Walter Mohr , Frank Hensel
发明人： Jochen Rueter , Simone Rehm , Joerg-Walter Mohr , Frank Hensel
IPC分类号： G06F11/27
CPC分类号： G06F11/27 , G01R31/31919 , G01R31/31935
摘要： Embodiments of the present invention provide an automatic test equipment. The automatic test equipment is configured to receive an input signal from a device under test and to write an information describing the input signal to a memory. The automatic test equipment is further configured to read the information describing the input signal from the memory and to provide an output signal for the device under test based on the information describing the input signal read from the memory.
摘要翻译：本发明的实施例提供一种自动测试设备。自动测试设备被配置为从被测设备接收输入信号，并将描述输入信号的信息写入存储器。自动测试设备还被配置为基于描述从存储器读取的输入信号的信息读取描述来自存储器的输入信号的信息，并为被测设备提供输出信号。

7. 发明授权

US08769363B2 Test apparatus 有权
标题翻译：测试仪器
公开(公告)号：US08769363B2
公开(公告)日：2014-07-01
申请号：US13403985
申请日：2012-02-24
申请人： Toshiyuki Negishi
发明人： Toshiyuki Negishi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31919 , G11C29/56004
摘要： Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.
摘要翻译：提供了一种包括多个图案输出部分的测试装置。在高速模式中，每个图形输出部输出对应于多个部分周期中的至少一个的图形数据，输入与图案输出部分输入的输入图案对应的图案数据和对应于输入图案的图案数据输入到其他模式输出段。

8. 发明授权

US08704573B2 Data latch circuit 有权
标题翻译：数据锁存电路
公开(公告)号：US08704573B2
公开(公告)日：2014-04-22
申请号：US13107478
申请日：2011-05-13
申请人： Hideyuki Suzawa
发明人： Hideyuki Suzawa
IPC分类号： H03K3/00
CPC分类号： G01R31/31919
摘要： A serial-format data signal is input to a data input terminal. Each of n (n represents an integer of two or more) multiple clock input terminals is configured to receive a clock signal as an input signal. An input flip-flop latches the data signal at each timing that corresponds to the corresponding clock signal. A serial/parallel converter converts the serial-format data signal into a parallel-format intermediate data signal using the corresponding clock signal. A data selector selects one from among the n intermediate data signals according to a selection signal.
摘要翻译：串行格式数据信号被输入到数据输入端。 n（n表示两个以上的整数）的多个时钟输入端子被配置为接收时钟信号作为输入信号。输入触发器在对应于相应时钟信号的每个定时锁存数据信号。串行/并行转换器使用相应的时钟信号将串行格式数据信号转换成并行格式的中间数据信号。数据选择器根据选择信号从n个中间数据信号中选择一个。

9. 发明授权

US08601325B2 Test data management system and method 失效
标题翻译：测试数据管理系统和方法
公开(公告)号：US08601325B2
公开(公告)日：2013-12-03
申请号：US13245877
申请日：2011-09-27
申请人： Zhi-Yong Zhao , Tai-Chen Wang , Lei Ye
发明人： Zhi-Yong Zhao , Tai-Chen Wang , Lei Ye
IPC分类号： G06F11/00
CPC分类号： G01R31/31919
摘要： In a test data management method, an electronic signal that needed to be tested of an electronic device is select. A predefined template file of a test report of the electronic signal is generated. Test data of the electronic signal is obtained from a test file, and is inserted into predetermined locations of the template file. The test report of the electronic signal is generated according to the template file and the inserted test data, and the test report is stored into a storage system of a computing device.
摘要翻译：在测试数据管理方法中，选择需要对电子设备进行测试的电子信号。生成电子信号的测试报告的预定模板文件。从测试文件获得电子信号的测试数据，并插入模板文件的预定位置。根据模板文件和插入的测试数据生成电子信号的测试报告，并将测试报告存储到计算设备的存储系统中。

10. 发明申请

US20130043899A1 PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS 有权
公开(公告)号：US20130043899A1
公开(公告)日：2013-02-21
申请号：US13657115
申请日：2012-10-22
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： H03K19/00
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

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