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    • 2. 发明授权
    • Charging/discharging circuit
    • 充电/放电电路
    • US4555655A
    • 1985-11-26
    • US592857
    • 1984-03-23
    • Tatsuo Tanaka
    • Tatsuo Tanaka
    • G05F1/618G05F1/56G05F1/585H03H11/24H03G3/00
    • H03H11/24G05F1/585
    • A charging/discharging circuit is formed of transistors Q1, Q2; resistors R1-R4; and a capacitor C. The series resistors R1, R2 are connected between the power supply line +Vcc and the circuit ground. The series resistors R3, R4 are connected between the line +Vcc and the circuit ground. The collector of NPN transistor Q1 is connected to +Vcc, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. The collector of PNP transistor Q1 is connected to the circuit ground, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. Capacitor C is connected in parallel to R2. The charged voltage of C is used as a reference potential VR for another linear circuit. Suppose that R1=R2, R3=R4 and +Vcc=10 V. When +Vcc rises from 0 V to 10 V but VR does not reach to 5 V, Q1 is forwardly biased so that C is quickly charged by the emitter current of Q1. When +Vcc falls from 10 V to 0 V but VR does not reach 0 V, Q2 is forwardly biased so that C is quickly discharged by the emitter current of Q2. When VR=5 V (stationary state), Q1 and Q2 are both cut-off, so that only small currents flow through the series circuits of R1, R2 and R3, R4. The time constant of (R1.vertline..vertline.R2).C can be made large so that VR is free from ripples of +Vcc.
    • 充电/放电电路由晶体管Q1,Q2形成; 电阻R1-R4; 和电容器C.串联电阻器R1,R2连接在电源线+ Vcc和电路接地之间。 串联电阻R3,R4连接在线路+ Vcc和电路接地之间。 NPN晶体管Q1的集电极连接到+ Vcc,其基极连接到R3和R4之间的结,其发射极耦合到R1和R2之间的连接处。 PNP晶体管Q1的集电极连接到电路地,其基极连接到R3和R4之间的结,其发射极耦合到R1和R2之间的连接处。 电容器C与R2并联连接。 C的充电电压用作另一线性电路的基准电位VR。 假设R1 = R2,R3 = R4和+ Vcc = 10V。当+ Vcc从0V升至10V但VR不达到5V时,Q1被正向偏置,使得C被发射极电流快速充电 Q1。 当+ Vcc从10V下降到0V而VR不达到0V时,Q2被向前偏置,使得C被Q2的发射极电流快速放电。 当VR = 5 V(静止状态)时,Q1和Q2都截止,只有小电流流过R1,R2和R3,R4的串联电路。 (R1||R2).C的时间常数可以变大,使得VR没有+ Vcc的波纹。
    • 3. 发明授权
    • Power supply circuit
    • 电源电路
    • US4459538A
    • 1984-07-10
    • US390874
    • 1982-06-22
    • Youichi AraiMasayuki Takagi
    • Youichi AraiMasayuki Takagi
    • G05F1/56G05F1/585G05F1/48
    • G05F1/585
    • A power supply circuit which comprises a first power source terminal for applying a plus voltage and a second power source terminal for applying a minus voltage. A first transistor is inserted between the first power source terminal and a load. A second transistor is inserted between a base of the first transistor and a ground potential and is controlled by the voltages applied to the first and second power source terminals. A capacitor is connected to the second power source and ground potential. A sequence of applying or cutting-off voltages to be applied to the load is predetermined even when a sequence of applying or cutting-off the voltages from said first and second power source terminals becomes erratic.
    • 一种电源电路,包括用于施加正电压的第一电源端子和用于施加负电压的第二电源端子。 第一晶体管插在第一电源端子和负载之间。 第二晶体管被插入在第一晶体管的基极和接地电位之间,并且被施加到第一和第二电源端子的电压控制。 电容器连接到第二电源和地电位。 即使当施加或切断来自所述第一和第二电源端子的电压的顺序变得不稳定时,施加或切断施加到负载的电压的顺序是预定的。