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1. 发明授权

US09965012B2 Multi-element memory device with power control for individual elements 有权
公开(公告)号：US09965012B2
公开(公告)日：2018-05-08
申请号：US15017395
申请日：2016-02-05
申请人： Rambus Inc.
发明人： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC分类号： G06F1/32 , G11C5/14 , G06F1/28 , G11C5/06 , G06F13/42
CPC分类号： G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
摘要： A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

2. 发明申请

US20170177301A1 ASYMMETRIC CHIP-TO-CHIP INTERCONNECT 审中-公开
公开(公告)号：US20170177301A1
公开(公告)日：2017-06-22
申请号：US15431421
申请日：2017-02-13
申请人： Micron Technology, Inc.
发明人： Timothy M. Hollis
IPC分类号： G06F5/06 , G06F13/42 , H04L12/40 , G06F13/38 , H04L29/08
CPC分类号： G06F5/06 , G06F13/38 , G06F13/385 , G06F13/4273 , H04L12/4013 , H04L25/0272 , H04L67/288 , H04Q2213/13036 , H04Q2213/13305
摘要： Methods and apparatus to transfer data between a first device and a second device, is disclosed. An apparatus according to various embodiments may comprise a first device and a second device. The first device may comprise at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device may comprise at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel.

3. 发明申请

US20150149672A1 CLOCKLESS VIRTUAL GPIO 有权
标题翻译：无时钟虚拟GPIO
公开(公告)号：US20150149672A1
公开(公告)日：2015-05-28
申请号：US14540366
申请日：2014-11-13
申请人： QUALCOMM Incorporated
发明人： Lalan Jee Mishra , Richard Dominic Wietfeldt , Mohit Kishore Prasad
IPC分类号： G06F13/42 , G06F9/455
CPC分类号： G06F13/4221 , G06F9/45533 , G06F13/4273
摘要： A virtual GPIO architecture for an integrated circuit is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.
摘要翻译：提供了一个用于集成电路的虚拟GPIO架构，既可以串行化虚拟GPIO信号，也可以反序列化虚拟GPIO信号，无需外部时钟。

4. 发明授权

US08913616B2 System-on-chip-based network protocol in consideration of network efficiency 有权
标题翻译：考虑到网络效率的基于系统的片上网络协议
公开(公告)号：US08913616B2
公开(公告)日：2014-12-16
申请号：US13640310
申请日：2010-10-22
申请人： Chan-Ho Lee
发明人： Chan-Ho Lee
IPC分类号： H04L12/28 , G06F13/42 , G06F15/78
CPC分类号： G06F13/4273 , G06F15/7825
摘要： An SoC-based system network protocol in consideration of network efficiency is disclosed. An MSB of a command signal containing an instruction defining information that is contained in a transfer signal transferred from an initiator to a destination via a channel or in a response signal transferred from the destination via the channel indicates that a highest priority is assigned to a transaction between the initiator and the destination in the network, when the instruction contained in the command signal corresponds to address information contained in the transfer signal and response information contained in the response signal, and indicates last data of a signal transferred between the initiator and the destination when the instruction contained in the command signal corresponds to control information contained in the transfer signal and data contained in the transfer signal and the response signal.
摘要翻译：考虑到网络效率的基于SoC的系统网络协议被公开。命令信号的MSB包含定义信息的指令，所述指令包含在经由信道或从目的地经由信道传送的响应信号中的从发起者传送到目的地的传送信号中的信息，表示将最高优先级分配给交易在网络中的发起者和目的地之间，当包含在命令信号中的指令对应于包含在传送信号中的地址信息和包含在响应信号中的响应信息，并且指示在发起者和目的地之间传送的信号的最后数据当包含在命令信号中的指令对应于包含在传送信号中的控制信息和包含在传送信号中的数据和响应信号时。

5. 发明授权

US08675679B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08675679B2
公开(公告)日：2014-03-18
申请号：US13330734
申请日：2011-12-20
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
摘要翻译：公开了一种通过总线进行通信的方法。总线包括写地址通道，写通道和读地址通道。该方法包括经由写入地址信道从发送设备发送地址到接收设备。该方法还包括经由读取地址信道经由写入信道和有效载荷的另一部分经由读取地址信道同时将一部分有效负载发送到接收设备。当经由总线同时发送有效负载的多个连续部分时，发送设备被配置为通过经由写入通道发送多个连续部分的第一顺序部分来通过读取地址信道给予写入信道的数据排序偏好，并且发送多个顺序部分的后续顺序部分经由读地址信道。

6. 发明授权

US08654634B2 Dynamically reassigning virtual lane resources 失效
标题翻译：动态重新分配虚拟通道资源
公开(公告)号：US08654634B2
公开(公告)日：2014-02-18
申请号：US11751119
申请日：2007-05-21
申请人： Kris M. Kendall , Calvin C. Paynton , Michael A. Perez
发明人： Kris M. Kendall , Calvin C. Paynton , Michael A. Perez
IPC分类号： H04L12/28
CPC分类号： G06F13/4273
摘要： A system and method for dynamically reassigning buffer space during to maximize IO performance of virtual lanes is set forth. More specifically, the system and method for dynamically reassigning buffer space takes buffer space from unused virtual lanes and reassigns the unused buffer space to used virtual lanes, e.g., when changes occur to an IO configuration. For example, in an embodiment that supports four virtual lanes where only two virtual lanes are in use, the system and method reassign the buffer space from the other two unused virtual lanes for use by the two virtual lanes in use.
摘要翻译：阐述了在最大化虚拟通道的IO性能期间动态地重新分配缓冲空间的系统和方法。更具体地，用于动态重新分配缓冲空间的系统和方法从未使用的虚拟通道获取缓冲空间，并且例如当IO配置发生变化时，将未使用的缓冲区重新分配给所使用的虚拟通道。例如，在支持四个虚拟通道的实施例中，其中只有两个虚拟通道正在使用中，该系统和方法重新分配来自另外两个未使用的虚拟通道的缓冲区空间，供使用中的两个虚拟通道使用。

7. 发明申请

US20130159584A1 DATA BUS INVERSION CODING 有权
标题翻译：数据总线反相编码
公开(公告)号：US20130159584A1
公开(公告)日：2013-06-20
申请号：US13330482
申请日：2011-12-19
申请人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
发明人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
IPC分类号： G06F13/28
CPC分类号： G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
摘要翻译：公开了涉及数据反转编码的技术。在一个实施例中，一种装置包括接口电路。接口电路被配置为执行包括使用反转编码方案编码的相应多个数据传输的第一和第二数据突发。在这样的实施例中，使用第一数据突发的最终数据传输对第二数据脉冲串的初始数据传输进行编码。在一些实施例中，第一和第二数据脉冲串对应于来自存储器PHY的存储器模块的连续写操作或连续读操作。

8. 发明申请

US20130028261A1 SYSTEM-ON-CHIP-BASED NETWORK PROTOCOL IN CONSIDERATION OF NETWORK EFFICIENCY 有权
标题翻译：基于系统的基于网络的网络协议考虑网络效率
公开(公告)号：US20130028261A1
公开(公告)日：2013-01-31
申请号：US13640310
申请日：2010-10-22
申请人： Chan-Ho Lee
发明人： Chan-Ho Lee
IPC分类号： H04L12/56
CPC分类号： G06F13/4273 , G06F15/7825
摘要： An SoC-based system network protocol in consideration of network efficiency is disclosed. An MSB of a command signal containing an instruction defining information that is contained in a transfer signal transferred from an initiator to a destination via a channel or in a response signal transferred from the destination via the channel indicates that a highest priority is assigned to a transaction between the initiator and the destination in the network, when the instruction contained in the command signal corresponds to address information contained in the transfer signal and response information contained in the response signal, and indicates last data of a signal transferred between the initiator and the destination when the instruction contained in the command signal corresponds to control information contained in the transfer signal and data contained in the transfer signal and the response signal.
摘要翻译：考虑到网络效率的基于SoC的系统网络协议被公开。命令信号的MSB包含定义信息的指令，所述指令包含在经由信道或从目的地经由信道传送的响应信号中的从发起者传送到目的地的传送信号中的信息，表示将最高优先级分配给交易在网络中的发起者和目的地之间，当包含在命令信号中的指令对应于包含在传送信号中的地址信息和包含在响应信号中的响应信息，并且指示在发起者和目的地之间传送的信号的最后数据当包含在命令信号中的指令对应于包含在传送信号中的控制信息和包含在传送信号中的数据和响应信号时。

9. 发明授权

US08107492B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08107492B2
公开(公告)日：2012-01-31
申请号：US11468908
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。

10. 发明申请

US20110078355A1 Radio-Control Board For Software-Defined Radio Platform 有权
标题翻译：软件定义无线电台无线电台
公开(公告)号：US20110078355A1
公开(公告)日：2011-03-31
申请号：US12571188
申请日：2009-09-30
申请人： Kun Tan , Jiansong Zhang , Yongguang Zhang
发明人： Kun Tan , Jiansong Zhang , Yongguang Zhang
IPC分类号： G06F13/14
CPC分类号： G06F13/4273 , G06F13/38 , G06F13/40 , H04B1/0007
摘要： A radio control board exchanges data with a radio frequency (RF) front end using a messaging protocol over an interface that includes separate data and control channels. Training data can also be passed over the interface for tuning the clock phase.
摘要翻译：无线电控制板通过包括单独的数据和控制信道的接口使用消息传递协议与射频（RF）前端交换数据。培训数据也可以通过接口传递，以调整时钟相位。

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