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1. 发明申请

US20190050702A1 SECURE SEMICONDUCTOR CHIP AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20190050702A1
公开(公告)日：2019-02-14
申请号：US16076473
申请日：2017-02-10
申请人： INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
发明人： Hyoung Ho KO , Chang-Sik YOO , Byong Deok CHOI
IPC分类号： G06K19/073 , G06Q20/34
CPC分类号： H04L63/0869 , G06F15/7807 , G06F15/7842 , G06F15/7853 , G06F21/55 , G06F21/556 , G06F21/57 , G06F21/60 , G06F21/602 , G06F21/74 , G06F21/85 , G06F2221/2149 , G06K19/07372 , G06Q20/341 , H04L9/321 , H04L9/3263 , H04L9/3278 , H04L2209/12
摘要： Disclosed is a secure semiconductor chip. When a physical attack such as a depackaging attack occurs, the semiconductor chip can detect the physical attack. A semiconductor chip according to one embodiment comprises an energy harvesting element inside a package. The energy harvesting element may comprise, for example, an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.

2. 发明授权

US09965393B2 Caching for heterogeneous processors 有权
公开(公告)号：US09965393B2
公开(公告)日：2018-05-08
申请号：US14977929
申请日：2015-12-22
申请人： Intel Corporation
发明人： Frank T. Hady , Mason Cabot , Mark B. Rosenbluth , John Beck
IPC分类号： G06F12/08 , G06F12/084 , G06F15/167 , G06F15/78 , G06F12/0815 , G06F12/0893
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

3. 发明授权

US09285793B2 Data processing unit including a scalar processing unit and a heterogeneous processor unit 有权
标题翻译：数据处理单元，包括标量处理单元和异构处理器单元
公开(公告)号：US09285793B2
公开(公告)日：2016-03-15
申请号：US13880473
申请日：2011-10-20
申请人： Ray McConnell , Paul Winser
发明人： Ray McConnell , Paul Winser
IPC分类号： G05B19/02 , G06T1/20 , G06F15/78 , G06F15/80 , H04L29/06
CPC分类号： G05B19/02 , G06F15/7842 , G06F15/8092 , G06T1/20 , H04L69/12 , Y02D10/13
摘要： A data processing unit combines a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration.
摘要翻译：数据处理单元组合标量处理器和包括向量处理阵列的异构处理器。矢量处理阵列包括可在单指令多数据配置中操作的多个向量处理器。

4. 发明申请

US20150081976A1 CACHING FOR HETEROGENEOUS PROCESSORS 审中-公开
标题翻译：缓存异步处理器
公开(公告)号：US20150081976A1
公开(公告)日：2015-03-19
申请号：US14319616
申请日：2014-06-30
申请人： Intel Corporation
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F15/78 , G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享高速缓存的多核处理器。

5. 发明授权

US08799579B2 Caching for heterogeneous processors 有权
标题翻译：异构处理器的缓存
公开(公告)号：US08799579B2
公开(公告)日：2014-08-05
申请号：US13766074
申请日：2013-02-13
申请人： Intel Corporation
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

6. 发明申请

US20140044157A1 MULTI-BAND INTERCONNECT FOR INTER-CHIP AND INTRA-CHIP COMMUNICATIONS 有权
标题翻译：多芯片互连和芯片间通信
公开(公告)号：US20140044157A1
公开(公告)日：2014-02-13
申请号：US13965077
申请日：2013-08-12
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： Mau-Chung Chang , Sai-Wang Tam , Gyung-Su Byun , Yanghyo Kim , Kanit Therdsteerasukdi , Jeremy Ir , Glenn Reinman , Jingsheng Cong
IPC分类号： H04L25/02 , H04L27/04
CPC分类号： H04L27/3483 , G06F15/7842 , G06F2213/0038 , G11C5/063 , G11C7/10 , G11C7/1057 , G11C7/1084 , H04L25/0274 , H04L27/04 , H04L45/60 , H04L2025/03388
摘要： Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.
摘要翻译：使用包含基带和一个或多个幅移键控（ASK）RF信道的多频带通信的存储器件进行通信的系统，装置，模块和方法，每个差分对的芯片外传输线路。描述了用于在微处理器或控制器和存储设备或模块之间以及在DIMM及其DRAM设备内以及在多个DIMM存储器模块之间进行接口的配置。

7. 发明申请

US20130305013A1 MICROPROCESSOR THAT MAKES 64-BIT GENERAL PURPOSE REGISTERS AVAILABLE IN MSR ADDRESS SPACE WHILE OPERATING IN NON-64-BIT MODE 有权
标题翻译：微处理器可在非64位模式下运行的MSR地址空间中提供64位通用寄存器
公开(公告)号：US20130305013A1
公开(公告)日：2013-11-14
申请号：US13874838
申请日：2013-05-01
申请人： VIA Technologies, Inc.
发明人： Mark John Ebersole
IPC分类号： G06F15/78
CPC分类号： G06F15/7842 , G06F9/30076 , G06F9/30112 , G06F9/30138 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/4401
摘要： A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes.
摘要翻译：微处理器包括实例化IA-32架构EDX和EAX GPR的硬件寄存器以及实例化英特尔64架构R8-R15 GPR的硬件寄存器。微处理器与每个R8-R15 GPR相关联，分别有独特的MSR地址。为了响应指定R8-R15 GPR之一的相应唯一MSR地址的IA-32架构RDMSR指令，微处理器读取硬件寄存器的内容，该硬件寄存器将R8-R15 GPR中指定的一个实例化到硬件寄存器实例化EDX：EAX寄存器。为了响应指定R8-R15 GPR之一的相应唯一MSR地址的IA-32架构WRMSR指令，微处理器写入硬件寄存器，将R8-R15 GPR中指定的一个实例化到硬件寄存器的内容实例化EDX：EAX寄存器。即使在非64模式下工作，微处理器也会这样做。

8. 发明授权

US08421500B2 Integrated circuit with stacked computational units and configurable through vias 失效
标题翻译：具有堆叠计算单元并可通过通孔进行配置的集成电路
公开(公告)号：US08421500B2
公开(公告)日：2013-04-16
申请号：US12952365
申请日：2010-11-23
申请人： Harry S. Barowski , Tim Niggemeier
发明人： Harry S. Barowski , Tim Niggemeier
IPC分类号： H03K19/177
CPC分类号： G06F15/80 , G06F15/7842 , H01L22/22 , H01L23/544 , H01L25/0657 , H01L2223/54433 , H01L2223/5444 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the second die. Sets of vertical vias that extend through the first, second, and third dies are connected to connect components of the first and second computational units and the memory unit. Multiplexers of the first and second computational units are configured to selectively couple the components to different ones of the sets of vertical vias responsive to respective control words for each of the first and third dies.
摘要翻译：一种用于制造三维集成电路的技术包括在包括第一计算单元的第一管芯上堆叠存储器单元。在这种情况下，存储器单元包括在第二管芯中。包括在第三管芯中的第二计算单元堆叠在第二管芯上。连接穿过第一，第二和第三管芯的垂直通孔的连接件连接到第一和第二计算单元和存储器单元的部件。第一和第二计算单元的多路复用器被配置为响应于用于第一和第三管芯中的每一个的相应控制字选择性地将组件耦合到垂直通孔中的不同组。

9. 发明申请

US20120297166A1 STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING AN INSTRUCTION SET OPTIMIZED TO MINIMIZE MEMORY FETCH OPERATIONS 有权
标题翻译：堆栈处理器使用具有最优化存储器操作的指令集的FERROELECTRIC随机存取存储器（F-RAM）
公开(公告)号：US20120297166A1
公开(公告)日：2012-11-22
申请号：US13467816
申请日：2012-05-09
申请人： Franck Fillere
发明人： Franck Fillere
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/7842 , G06F9/30134 , G06F12/0804 , G06F12/0875 , G06F15/7807
摘要： A stack processor using a non-volatile, ferroelectric random access memory (F-RAM) for both code and data space. The stack processor is operative in response to as many as 64 possible instructions based upon a 16 bit word. Each of the instructions in the 16 bit word comprises 3 five bit instructions and a 16th bit which is applicable to each of the 3 five bit instructions thereby making each instruction effectively 6 bits wide.
摘要翻译：使用非易失性，铁电随机存取存储器（F-RAM）的堆栈处理器，用于代码和数据空间。堆栈处理器响应于基于16位字的多达64个可能的指令来操作。 16位字中的每个指令都包括3位5位指令和第16位，可适用于3位5位指令中的每一位，从而使每个指令有效地为6位宽。

10. 发明申请

US20120297130A1 STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR BOTH CODE AND DATA SPACE 有权
标题翻译：使用用于两个代码和数据空间的FERROELECTRIC RANDOM ACCESS MEMORY（F-RAM）的堆栈处理器
公开(公告)号：US20120297130A1
公开(公告)日：2012-11-22
申请号：US13467831
申请日：2012-05-09
申请人： Franck Fillere
发明人： Franck Fillere
IPC分类号： G06F12/00
CPC分类号： G06F13/16 , G06F9/44 , G06F15/78 , G06F15/7842
摘要： A stack processor using a ferroelectric random access memory (F-RAM) for both code and data space which presents the advantages of easy stack pointer management inasmuch as the stack pointer is itself a memory address. Further, the time for saving all critical registers to memory is also minimized in that all registers are already maintained in non-volatile F-RAM per se.
摘要翻译：使用用于代码和数据空间的铁电随机存取存储器（F-RAM）的堆栈处理器，其呈现易于堆栈指针管理的优点，因为堆栈指针本身是存储器地址。此外，将所有关键寄存器保存到存储器的时间也被最小化，因为所有寄存器已经被维护在非易失性F-RAM本身。

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