专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10038444B2 Reconfigurable system-on-chip and related methods 有权
公开(公告)号：US10038444B2
公开(公告)日：2018-07-31
申请号：US15458692
申请日：2017-03-14
申请人： STMicroelectronics S.r.l.
发明人： Salvatore Marco Rosselli , Daniele Mangano , Riccardo Condorelli
IPC分类号： G06F7/38 , H03K19/00 , H03K19/177 , H03K19/173 , G06F15/78
CPC分类号： H03K19/0008 , G06F15/7867 , G06F2209/507 , H03K19/1737 , H03K19/1776
摘要： A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

2. 发明申请

US20170132050A1 Selecting Processor Micro-Threading Mode 有权
公开(公告)号：US20170132050A1
公开(公告)日：2017-05-11
申请号：US14948277
申请日：2015-11-21
申请人： International Business Machines Corporation
发明人： Paul Mackerras
IPC分类号： G06F9/50 , G06F9/455
CPC分类号： G06F9/5083 , G06F9/223 , G06F9/30189 , G06F9/3851 , G06F9/45533 , G06F9/45558 , G06F9/5077 , G06F2009/4557 , G06F2009/45575 , G06F2209/507
摘要： An approach is provided to dynamically select a micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the processor is running a hypervisor. The approach sets a core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a light load level, sets the core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the light load level, and sets the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core is at a high load level.

3. 发明申请

US20170132049A1 Selecting Processor Micro-Threading Mode 有权
公开(公告)号：US20170132049A1
公开(公告)日：2017-05-11
申请号：US14938011
申请日：2015-11-11
申请人： International Business Machines Corporation
发明人： Paul Mackerras
IPC分类号： G06F9/50 , G06F9/22 , G06F9/455
CPC分类号： G06F9/5083 , G06F9/223 , G06F9/30189 , G06F9/3851 , G06F9/45533 , G06F9/45558 , G06F9/5077 , G06F2009/4557 , G06F2009/45575 , G06F2209/507
摘要： An approach is provided to dynamically select a micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the processor is running a hypervisor. The approach sets a core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a light load level, sets the core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the light load level, and sets the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core is at a high load level.

4. 发明申请

US20170132003A1 System and Method for Hardware Multithreading to Improve VLIW DSP Performance and Efficiency 审中-公开
公开(公告)号：US20170132003A1
公开(公告)日：2017-05-11
申请号：US14937093
申请日：2015-11-10
申请人： Futurewei Technologies, Inc.
发明人： Tong Sun , Ying Xu , Weizhong Chen
IPC分类号： G06F9/30 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/3853 , G06F9/3889 , G06F9/3891 , G06F9/5027 , G06F2209/507 , Y02D10/22
摘要： A system and method of hardware multithreading in VLIW DSPs includes an instruction fetch and dispatch unit, a plurality of program control units coupled to the instruction fetch and dispatch unit, a plurality of function units coupled to the plurality of program control units, and a mode control unit coupled to the function units and the program control units, the mode control unit configured to dynamically organize the plurality of function units and the plurality of program control units into one or more threads, each thread comprising a program control of the plurality of program control units and a subset of the plurality of function units.

5. 发明授权

US09634669B2 Reconfigurable system-on-chip and related methods 有权
公开(公告)号：US09634669B2
公开(公告)日：2017-04-25
申请号：US14971150
申请日：2015-12-16
申请人： STMICROELECTRONICS S.R.L.
发明人： Salvatore Marco Rosselli , Daniele Mangano , Riccardo Condorelli
IPC分类号： H03K19/177 , G06F15/78 , H03K19/00
CPC分类号： H03K19/0008 , G06F15/7867 , G06F2209/507 , H03K19/1737 , H03K19/1776
摘要： A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

6. 发明授权

US09606800B1 Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture 有权
公开(公告)号：US09606800B1
公开(公告)日：2017-03-28
申请号：US13836145
申请日：2013-03-15
申请人： Marvell International Ltd.
发明人： Tom Hameenanttila , R. Frank O'Bleness , Sujat Jamil , Joseph Delgross
IPC分类号： G06F9/30 , G06F11/07 , G06F9/38 , G06F9/50 , G06F9/48
CPC分类号： G06F9/30145 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/4881 , G06F9/5011 , G06F9/5061 , G06F11/0754 , G06F2209/507
摘要： A microprocessor includes a front end module and a schedule queue module. The front end module is configured to retrieve first instructions, corresponding to a first thread, from an instruction cache, and retrieve second instructions, corresponding to a second thread, from the instruction cache. The front end module is also configured to decode the first instructions into first decoded instructions, and decode the second instructions into second decoded instructions. The schedule queue module is configured to selectively store the first decoded instructions and the second decoded instructions from the front end module and, for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module. The schedule queue is further configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a threshold.

7. 发明授权

US09400657B2 Dynamic management of a transaction retry indication 有权
标题翻译：动态管理事务重试指示
公开(公告)号：US09400657B2
公开(公告)日：2016-07-26
申请号：US13868392
申请日：2013-04-23
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Brian W. Thompto
IPC分类号： G06F9/46 , G06F9/44 , G06F9/30 , G06F9/38 , G06F9/50
CPC分类号： G06F9/44 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Embodiments relate to dynamic management of a transaction retry indication. One aspect is a system that includes a transactional facility configured to support transactions that effectively delay committing stores to memory or results to an architectural state until transaction completion, and a processor configured to identify a transaction abort reason associated with an aborted transaction of an initiating program. Transaction success and transaction abort history are tracked. Based on determining by the processor that the transaction abort reason was caused by the initiating program, a retry indication is assigned based on a static mapping of the transaction abort reason. Based on determining by the processor that the transaction abort reason was not caused by the initiating program, the retry indication is assigned based on a retry process using the transaction abort reason, the transaction abort history, and a current processor configuration.
摘要翻译：实施例涉及事务重试指示的动态管理。一个方面是一种系统，其包括事务设施，其被配置为支持将事务有效延迟到存储器或结果到事务完成之前的架构状态的事务;以及处理器，被配置为识别与启动程序的中止事务相关联的事务中止原因。跟踪交易成功和交易中止历史。基于由处理器确定事务中止原因是由启动程序引起的，基于事务中止原因的静态映射来分配重试指示。基于由处理器确定事务中止原因不是由启动程序引起的，基于使用事务中止原因，事务中止历史和当前处理器配置的重试过程来分配重试指示。

8. 发明授权

US09250961B2 Task execution in a SIMD processing unit 有权
标题翻译：在SIMD处理单元中执行任务
公开(公告)号：US09250961B2
公开(公告)日：2016-02-02
申请号：US14572944
申请日：2014-12-17
申请人： Imagination Technologies Limited
发明人： John Howson , Jonathan Redshaw , Yoong Chert Foo
IPC分类号： G06F9/48 , G06F9/38 , G06F15/80 , G06F9/30 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30036 , G06F9/3822 , G06F9/3836 , G06F9/3887 , G06F9/4881 , G06F15/8007 , G06F2209/507
摘要： A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
摘要翻译： SIMD处理单元处理多个任务，每个任务包括多达预定的最大数目的工作项。任务的工作项目被安排用于对各个数据项执行公共的指令序列。数据项被排列成块，其中一些块包括至少一个无效数据项。与无效数据项相关的工作项是无效的工作项。 SIMD处理单元包括一组处理通道，其被配置为在多个处理循环中执行特定任务的工作项目的指令。控制模块基于工作项的有效性将工作项目组合到任务中，使得特定任务的无效工作项在时间上跨越处理通道进行对齐。以这种方式，可以减少由于无效的工作项造成的浪费的处理槽的数量。

9. 发明申请

US20150212858A1 MANAGEMENT OF RESOURCES WITHIN A COMPUTING ENVIRONMENT 有权
标题翻译：在计算环境中的资源管理
公开(公告)号：US20150212858A1
公开(公告)日：2015-07-30
申请号：US14684773
申请日：2015-04-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/50 , G06F9/455 , G06F9/48
CPC分类号： G06F9/5038 , G06F9/38 , G06F9/45533 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F9/5016 , G06F9/5077 , G06F2009/45591 , G06F2209/483 , G06F2209/5021 , G06F2209/504 , G06F2209/507 , G06F2209/508 , Y02B70/30 , Y02D10/22
摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
摘要翻译：计算环境中的资源例如通过硬件控制器进行管理，硬件控制器控制从用于执行线程的一个或多个资源池中调度资源。所述控制包括基于所述池中的资源相对于相关联的资源使用阈值的当前使用情况，将资源从所述池有条件地调度到所述计算环境的一个或多个低优先级线程。该管理还包括监视从该池到该计算环境的一个或多个高优先级线程的资源调度，并且基于该监视，动态地调整在从池中有条件地分派资源中使用的资源使用阈值）到低优先级线程。

10. 发明申请

US20150169370A1 Task Execution in a SIMD Processing Unit 有权
标题翻译： SIMD处理单元中的任务执行
公开(公告)号：US20150169370A1
公开(公告)日：2015-06-18
申请号：US14572944
申请日：2014-12-17
申请人： Imagination Technologies Limited
发明人： John Howson , Jonathan Redshaw , Yoong Chert Foo
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06T1/20 , G06F9/30036 , G06F9/3822 , G06F9/3836 , G06F9/3887 , G06F9/4881 , G06F15/8007 , G06F2209/507
摘要： A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
摘要翻译： SIMD处理单元处理多个任务，每个任务包括多达预定的最大数目的工作项。任务的工作项目被安排用于对各个数据项执行公共的指令序列。数据项被排列成块，其中一些块包括至少一个无效数据项。与无效数据项相关的工作项是无效的工作项。 SIMD处理单元包括一组处理通道，其被配置为在多个处理循环中执行特定任务的工作项目的指令。控制模块基于工作项的有效性将工作项目组合到任务中，使得特定任务的无效工作项在时间上跨越处理通道进行对齐。以这种方式，可以减少由于无效的工作项造成的浪费的处理槽的数量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式