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1. 发明授权

US09632901B2 Page resolution status reporting 有权
公开(公告)号：US09632901B2
公开(公告)日：2017-04-25
申请号：US14846870
申请日：2015-09-07
申请人： Mellanox Technologies Ltd.
发明人： Shlomo Raikin , Shachar Raindel , Noam Bloch , Liran Liss
IPC分类号： G06F11/30 , G06F12/10 , G06F13/16 , G06F13/38 , G06F12/08 , G06F12/1009 , G06F12/109 , G06F12/0891
CPC分类号： G06F11/3065 , G06F12/0891 , G06F12/1009 , G06F12/109 , G06F13/1663 , G06F13/385 , G06F2212/653 , G06F2212/657
摘要： A method for data transfer includes receiving in a data transfer operation data to be written by a peripheral device to a specified virtual address in a random access memory (RAM) of a host computer. Upon receiving the data, it is detected that a page that contains the specified virtual address is marked as not present in a page table of the host computer. The peripheral device receives a notification that the page is not present and an estimate of a length of time that will be required to make the page available and selects a mode for handling of the data transfer operation depending upon the estimate.

2. 发明申请

US20160253259A1 MIXED CACHE MANAGEMENT 有权
标题翻译：混合高速缓存管理
公开(公告)号：US20160253259A1
公开(公告)日：2016-09-01
申请号：US15032636
申请日：2013-10-29
申请人： HUA ZHONG UNIVERSITY OF SCIENCE TECHNOLOGY
发明人： Hai JIN , Xuanhua SHI , Song WU , Xin YU
IPC分类号： G06F12/08 , G06F12/12 , G06F12/10
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0891 , G06F12/1009 , G06F12/1054 , G06F12/123 , G06F2212/604 , G06F2212/653 , Y02D10/13
摘要： A mixed cache is indexed to main memory and page coloring is applied to map main memory to virtual memory. A nursery array and a mature array are indexed to virtual memory. An access to a virtual page from the mixed cache is recorded by determining an index and a tag of an array address based on a virtual address, following the index to corresponding rows in the nursery and the mature arrays, and determining if the tag in the array address matches any tag in the rows. When there is a match to a tag in the rows, an access count in a virtual page entry corresponding to the matched tags is incremented. When there is no match, a virtual page entry in the row in the nursery array is written with the tag in the array address and an access count in the entry is incremented.
摘要翻译：将混合高速缓存索引到主内存，并应用页面着色将主内存映射到虚拟内存。托儿所阵列和成熟阵列被索引到虚拟内存。通过根据托儿所和成熟阵列中的相应行的索引确定基于虚拟地址的数组地址的索引和标签来记录来自混合高速缓存的虚拟页面的访问，以及确定是否在数组地址匹配行中的任何标记。当与行中的标签匹配时，对应于匹配标签的虚拟页面条目中的访问计数增加。当没有匹配时，托盘数组中的行中的虚拟页条目被写入数组地址中的标签，并且条目中的访问计数增加。

3. 发明授权

US08966171B2 Access optimization method for main memory database based on page-coloring 有权
标题翻译：基于页面着色的主内存数据库的访问优化方法
公开(公告)号：US08966171B2
公开(公告)日：2015-02-24
申请号：US13514291
申请日：2012-05-16
申请人： Yan-Song Zhang , Shan Wang , Xuan Zhou , Min Jiao , Zhan-Wei Wang
发明人： Yan-Song Zhang , Shan Wang , Xuan Zhou , Min Jiao , Zhan-Wei Wang
IPC分类号： G06F12/10
CPC分类号： G06F12/1045 , G06F2212/653
摘要： An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the data pages are grouped by page-color, and then all the data pages of the weak locality dataset are scanned in a sequence of page-color grouping. Further, a number of memory pages having the same page-color are preset as a page-color queue, in which the page-color queue serves as a memory cache before a memory page is loaded into a CPU cache; the data page of the weak locality dataset first enters the page-color queue in an asynchronous mode, and is then loaded into the CPU cache to complete data processing. Accordingly, cache conflicts between datasets with different data locality strengths can be effectively reduced.
摘要翻译：描述了基于页面着色的主存储数据库的访问优化方法。弱位置数据集的所有数据页的访问序列按页面颜色排序，所有数据页按页面颜色分组，然后按照页面颜色顺序扫描弱位置数据集的所有数据页面，颜色分组。此外，将具有相同页面颜色的多个存储器页面预设为页面颜色队列，其中在将存储器页面加载到CPU高速缓存之前，页面颜色队列用作存储器高速缓存; 弱位置数据集的数据页首先以异步模式进入页面颜色队列，然后加载到CPU缓存中以完成数据处理。因此，可以有效地减少具有不同数据局部性强度的数据集之间的缓存冲突。

4. 发明申请

US20100250890A1 MANAGING WORKING SET USE OF A CACHE VIA PAGE COLORING 有权
标题翻译：管理工作集通过页面着色使用高速缓存
公开(公告)号：US20100250890A1
公开(公告)日：2010-09-30
申请号：US12781172
申请日：2010-05-17
申请人： Bradford Beckmann , Bradley M. Waters
发明人： Bradford Beckmann , Bradley M. Waters
IPC分类号： G06F12/02
CPC分类号： G06F12/1054 , G06F12/0842 , G06F2212/653
摘要： A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.
摘要翻译：处理器缓存由一组不同的页面颜色索引。使用页面着色来控制不同工作集使用此缓存。指令和/或工作集的数据的虚拟地址的翻译被限制为其页面颜色在不同页面颜色组的子组中的物理地址。

5. 发明授权

US06977657B2 Addressing a cache 有权
标题翻译：寻址缓存
公开(公告)号：US06977657B2
公开(公告)日：2005-12-20
申请号：US10214643
申请日：2002-08-08
申请人： Benoit Belley
发明人： Benoit Belley
IPC分类号： G06F12/08 , G06F12/10 , G09G5/39 , G09G5/36
CPC分类号： G06F12/1045 , G06F12/0897 , G06F2212/653
摘要： A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.
摘要翻译：数据处理系统具有主存储器和一个或多个高速缓存。缓存来自主存储器的数据，同时减轻地址模式依赖性的影响。主存储器物理地址在操作系统的控制下被转换为主存储器虚拟地址。翻译发生在逐页的基础上，使得一些虚拟地址位与一些物理地址位相同。选择一部分相同的地址位，并从所选择的部分生成高速缓存偏移值。数据从高速缓存偏移值导出的偏移位置写入高速缓存。

6. 发明申请

US20050188157A1 Memory mapping to reduce cache conflicts in multiprocessor sytems 失效
标题翻译：内存映射以减少多处理器系统中的缓存冲突
公开(公告)号：US20050188157A1
公开(公告)日：2005-08-25
申请号：US10782362
申请日：2004-02-19
申请人： Sujatha Kashyap
发明人： Sujatha Kashyap
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F2212/653
摘要： Methods, systems, and computer program products are disclosed for mapping a virtual memory page to a real memory page frame in a multiprocessing environment that supports a multiplicity of operating system images. Typical embodiments include retrieving into an operating system image, from memory accessible to a multiplicity of operating system images, a most recently used cache color for a cache, where the cache is shared by the operating system image with at least one other operating system image; selecting a new cache color in dependence upon the most recently used cache color; selecting in the operating system image a page frame in dependence upon the new cache color; and storing in the memory the new cache color as the most recently used cache color for the cache.
摘要翻译：公开了方法，系统和计算机程序产品，用于在支持多个操作系统图像的多处理环境中将虚拟存储器页面映射到实际存储器页面帧。典型的实施例包括从多个操作系统图像可访问的存储器检索操作系统映像，用于高速缓存的最近使用的高速缓存颜色，其中高速缓存由至少一个其他操作系统映像由操作系统映像共享; 根据最近使用的缓存颜色选择新的缓存颜色; 根据新的高速缓存颜色在操作系统映像中选择页面帧; 并将新的高速缓存颜色存储在存储器中作为高速缓存的最近使用的高速缓存颜色。

7. 发明授权

US6026475A Method for dynamically remapping a virtual address to a physical address to maintain an even distribution of cache page addresses in a virtual address space 失效
标题翻译：将虚拟地址动态地重新映射到物理地址以维持虚拟地址空间中的高速缓存页地址的均匀分布的方法
公开(公告)号：US6026475A
公开(公告)日：2000-02-15
申请号：US978932
申请日：1997-11-26
申请人： Larry William Woodman
发明人： Larry William Woodman
IPC分类号： G06F11/34 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/1054 , G06F11/3452 , G06F12/10 , G06F12/023 , G06F12/0864 , G06F2201/81 , G06F2201/815 , G06F2201/835 , G06F2201/88 , G06F2201/885 , G06F2212/653
摘要： A method and apparatus for dynamically updating virtual to physical address mappings in order to reduce cache thrashing is disclosed in an example computer system having a memory apportioned into a number of pages. A cache is included in the computer system to store a subset of the pages of memory. Each of the pages of memory is addressed by a physical address that includes a cache page address portion. The pages of cache memory are accessed using a cache page address, which corresponds to the cache page address portion of the physical address of a corresponding page of memory. The disclosed system monitors the activity of virtual addresses and uses the activity of virtual addresses to increment cache page address activity counters. The cache page address activity counters are monitored to identify those cache page addresses that are frequently being accessed within a process to identify potential performance problems, such as thrashing. When a cache page address activity count has exceeded a pre-determined threshold, a virtual address associated with that cache page address is mapped to a different physical address having a different cache page address. The new cache page address that is selected for remapping purposes is selected to maintain an even distribution of cache page addresses on a system and process level. The physical page formerly mapped to the virtual address that was associated with a highly active cache page address is returned to a free list of the system, for use by another process. With such an arrangement, adjustments may be made to the virtual to physical translations during execution of a given process in order to improve the overall performance of the process and the overall system.
摘要翻译：在具有分配到多页的存储器的示例性计算机系统中公开了用于动态更新虚拟到物理地址映射以减少高速缓存颠簸的方法和装置。计算机系统中包含缓存以存储内存页面的一部分。存储器的每一页由包括高速缓存页地址部分的物理地址寻址。使用与对应的存储器页面的物理地址的高速缓存页地址部分对应的高速缓存页地址来访问高速缓冲存储器的页面。所公开的系统监视虚拟地址的活动，并使用虚拟地址的活动来增加高速缓存页地址活动计数器。监视缓存页面地址活动计数器以识别在进程中经常被访问的那些缓存页面地址，以识别潜在的性能问题，例如抖动。当高速缓存页地址活动计数超过预定阈值时，与该高速缓存页地址相关联的虚拟地址被映射到具有不同高速缓存页地址的不同物理地址。选择用于重新映射目的的新的缓存页面地址是为了在系统和进程级别上保持高速缓存页面地址的均匀分布。以前映射到与高活动缓存页面地址相关联的虚拟地址的物理页面将返回到系统的空闲列表，供其他进程使用。通过这样的布置，可以在给定处理的执行期间对虚拟到物理的翻译进行调整，以便改进过程和整个系统的整体性能。

8. 发明授权

US11853227B2 Data processing apparatus and method for performing address translation 有权
公开(公告)号：US11853227B2
公开(公告)日：2023-12-26
申请号：US17242729
申请日：2021-04-28
申请人： Arm Limited
发明人： Charles Andrew Giefer , Alexander Donald Charles Chadwick
IPC分类号： G06F12/10 , G06F12/1045 , G06F12/02 , G06F12/1009 , G06F12/1036
CPC分类号： G06F12/1045 , G06F12/0238 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F12/1063 , G06F2212/651 , G06F2212/653 , G06F2212/7201
摘要： There is provided a data processing apparatus and method of data processing. The data processing apparatus comprises storage circuitry to store a hierarchy of page tables comprising an intermediate level page table. Each entry of the intermediate level page table comprises base address information of a next level page table and control information indicating whether an addressing function has been applied to reorder physical storage locations of entries of the next level page table. Address translation circuitry is provided to perform address translations in response to receipt of a virtual address by performing a lookup in a next level page table dependent on the base address information and a page table index from the virtual address. When the control information indicates that the addressing function has been applied, the lookup is performed at a modified storage location generated by applying the addressing function to the page table index.

9. 发明授权

US10642744B2 Memory type which is cacheable yet inaccessible by speculative instructions 有权
公开(公告)号：US10642744B2
公开(公告)日：2020-05-05
申请号：US16022274
申请日：2018-06-28
申请人： NVIDIA Corporation
发明人： Darrell D. Boggs , Ross Segelken , Mike Cornaby , Nick Fortino , Shailender Chaudhry , Denis Khartikov , Alok Mooley , Nathan Tuck , Gordon Vreugdenhil
IPC分类号： G06F12/0875 , G06F9/38 , G06F12/0888 , G06F12/0811 , G06F12/1027 , G06F12/1009
CPC分类号： G06F12/0875 , G06F9/3842 , G06F12/0811 , G06F12/0888 , G06F12/1009 , G06F12/1027 , G06F2212/1052 , G06F2212/452 , G06F2212/507 , G06F2212/653
摘要： An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

10. 发明授权

US10002080B2 Memory system address modification policies 有权
公开(公告)号：US10002080B2
公开(公告)日：2018-06-19
申请号：US14143369
申请日：2013-12-30
申请人： Michael Henry Kass
发明人： Michael Henry Kass
IPC分类号： G06F12/10 , G06F12/1045 , G06F12/121
CPC分类号： G06F12/10 , G06F12/1045 , G06F12/121 , G06F2212/653
摘要： A memory system implements a plurality of virtual address modification policies and optionally a plurality of cache eviction policies. Virtual addresses are optionally, selectively, and/or conditionally modified by the memory system in accordance with a plurality of virtual address modification policies. The virtual address modification policies include no modification, modification according to two-dimensional Morton ordering, and modification according to three-dimensional Morton ordering. For example, in response to a reference to a particular virtual address, the particular virtual address is modified according to two-dimensional Morton ordering so that at least two elements in a same column and distinct respective rows of a two-dimensional data structure are loaded into a same cache line and/or are referenced via a same page table entry.

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