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1. 发明申请

US20190236228A1 CO-SIMULATION SYSTEM WITH DELAY COMPENSATION AND METHOD FOR CONTROL OF CO-SIMULATION SYSTEM 审中-公开
公开(公告)号：US20190236228A1
公开(公告)日：2019-08-01
申请号：US16259439
申请日：2019-01-28
申请人： Volvo Car Corporation
发明人： Edo DRENTH
IPC分类号： G06F17/50 , F02D41/14
CPC分类号： G06F17/5022 , F02D41/1401 , F02D2041/1437 , F02D2250/14 , G06F17/5095 , G06F2217/86 , G09B23/10 , G09B25/02
摘要： A method of providing stable communication between subsystems in a co-simulation system, including providing a signal S1 describing an output angular velocity of a rotating body of the first physical system; filtering the signal S1 using a continuous moving average, CMA, filter; and forming a time discrete first output signal S1*. In a second subsystem the signal S1* is received and the angular velocity described by S1* is applied to the second physical system. A response signal S2* describes a torque generated by the second subsystem. The response signal S2* is received by the first subsystem where a time discrete feedback signal SF* is formed based on the difference between the response signal S2* and a time discrete damping signal SD*.

2. 发明申请

US20170132344A1 MICRO-BENCHMARK ANALYSIS OPTIMIZATION FOR MICROPROCESSOR DESIGNS 审中-公开
公开(公告)号：US20170132344A1
公开(公告)日：2017-05-11
申请号：US15291459
申请日：2016-10-12
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： Haowei Zhang , Xiaoying Shen , Sebastian Turullols
IPC分类号： G06F17/50 , G06F17/16 , G06F17/11
CPC分类号： G06F17/5036 , G06F17/11 , G06F17/16 , G06F17/5009 , G06F17/5031 , G06F17/5081 , G06F2217/84 , G06F2217/86
摘要： Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

3. 发明授权

US09646120B1 Method and system for trace compaction during emulation of a circuit design 有权
公开(公告)号：US09646120B1
公开(公告)日：2017-05-09
申请号：US15158933
申请日：2016-05-19
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： Beshara Elmufdi , Mitchell G. Poplack , Viktor Salitrennik
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/68 , G06F2217/86
摘要： The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

4. 发明授权

US09501594B2 Graphical design verification environment generator 有权
公开(公告)号：US09501594B2
公开(公告)日：2016-11-22
申请号：US14565636
申请日：2014-12-10
申请人： Vtool Ltd.
发明人： Hagai Arbel , Asi Lifshitz
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5009 , G06F17/5022 , G06F17/5036 , G06F17/5081 , G06F2217/86
摘要： A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.

5. 发明授权

US09483603B2 Micro-benchmark analysis optimization for microprocessor designs 有权
标题翻译：微处理器设计的微基准分析优化
公开(公告)号：US09483603B2
公开(公告)日：2016-11-01
申请号：US14293763
申请日：2014-06-02
申请人： Oracle International Corporation
发明人： Haowei Zhang , Xiaoying Shen , Sebastian Turullols
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/11 , G06F17/16 , G06F17/5009 , G06F17/5031 , G06F17/5081 , G06F2217/84 , G06F2217/86
摘要： Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.
摘要翻译：实施例包括用于优化微处理器设计的微基准分析的系统和方法。例如，实施例寻求生成一组微基准和相关联的加权因子，其可以用于以对于细粒度（例如，RTL）模拟）有效地定义加权聚合工作负载条件，其方式是足够的代理预测商业工作量情况。微型基准测试套件可以比商业工作量更高效地模拟，因此使用微型基准套件作为商业工作负载的代理可以提供许多好处，包括更有效的迭代设计。

6. 发明申请

US20160203244A1 METHOD AND SYSTEM FOR ASSIGNING A SIGNAL OF A SYMBOL-BASED PROGRAM TO AN I/O FUNCTIONALITY OF A TARGET HARDWARE UNIT 审中-公开
标题翻译：用于将基于符号的程序的信号分配给目标硬件单元的I / O功能的方法和系统
公开(公告)号：US20160203244A1
公开(公告)日：2016-07-14
申请号：US14593709
申请日：2015-01-09
申请人： dSPACE digital signal processing and control engineering GmbH
发明人： Frank MERTENS , Dirk BERNECK , Martin KRONMUELLER , Sebastian SCHULTE , Henrik SUNDER , Frank SCHUETTE
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F8/30 , B60W2050/0002 , G06F8/20 , G06F17/5045 , G06F17/5095 , G06F2217/86
摘要： A computer-based system and method for assigning at least one signal of a symbol-based program to at least one I/O functionality of a target hardware unit is provided. A modeling tool has a symbol-based program with the signal that is to be assigned. The signal to be assigned of the symbol-based program and the at least one I/O functionality of the target hardware unit are specified in a configuration tool. Using the modeling tool, an I/O functionality of the target hardware unit is assigned in the symbol-based program to the signal that is to be assigned. A signal assignment information item is generated in the modeling tool from this assignment. The signal assignment information item is transmitted from the modeling tool to the configuration tool, and the configuration tool takes over the assignment to the I/O functionality of the target hardware unit of the signal to be assigned of the symbol-based program according to the signal assignment information item.
摘要翻译：提供了一种用于将基于符号的程序的至少一个信号分配给目标硬件单元的至少一个I / O功能的基于计算机的系统和方法。建模工具具有基于符号的程序，其中要分配的信号。在配置工具中指定要分配的基于符号的程序的信号和目标硬件单元的至少一个I / O功能。使用建模工具，将基于符号的程序中的目标硬件单元的I / O功能分配给要分配的信号。在该分配中，在建模工具中生成信号分配信息项。信号分配信息项目从建模工具发送到配置工具，配置工具根据基于符号的程序分配给要分配的信号的目标硬件单元的I / O功能，信号分配信息项目。

7. 发明授权

US09372772B1 Co-verification—of hardware and software, a unified approach in verification 有权
标题翻译：硬件和软件的协同验证，统一的验证方法
公开(公告)号：US09372772B1
公开(公告)日：2016-06-21
申请号：US14671993
申请日：2015-03-27
申请人： XPLIANT, Inc
发明人： Mohan Balan , Harish Krishnamoorthy , Nimalan Siva , Kishore Badari Atreya
IPC分类号： G06F11/27 , G06F9/45 , G06F17/50 , G06F9/44
CPC分类号： G06F11/27 , G06F8/427 , G06F8/71 , G06F11/261 , G06F17/5022 , G06F17/505 , G06F2217/86
摘要： A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.
摘要翻译：本文描述了共同验证方法和系统。共同验证方法能够同时验证软件和硬件。限制被提供给产生编程值的软件编译器。来自验证测试台的编程值和激励被用于测试诸如微处理器之类的设计。

8. 发明申请

US20150294054A1 Incremental Functional Verification of a Circuit Design 有权
标题翻译：电路设计的增量功能验证
公开(公告)号：US20150294054A1
公开(公告)日：2015-10-15
申请号：US14324004
申请日：2014-07-03
申请人： Synopsys, Inc.
发明人： Raj Shekher Mitra , Amit Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/86
摘要： A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.
摘要翻译：公开了一种用于验证计算机芯片设计的实现的系统和方法。接收包括一个或多个解释性计算机编程语言模块和一个或多个硬件描述语言（HDL）模块的设计。当其中一个解释性编程语言模块请求与其中一个HDL模块进行通信时，HDL模块被使能，并且来自解释性编程语言模块的输入参数被流水线化到HDL模块中。从HDL模块接收流水线输出数据。接收到的输出数据被格式化并返回到解释性编程语言模块。

9. 发明申请

US20150294049A1 BRAKE HILS SYSTEM FOR A RAILWAY VEHICLE 有权
标题翻译：用于铁路车辆的制动蹄系统
公开(公告)号：US20150294049A1
公开(公告)日：2015-10-15
申请号：US14684454
申请日：2015-04-13
申请人： Konkuk University Industrial Cooperation Corp.
发明人： Chul-Goo KANG , Nam Jin LEE , Dong-Chan LEE
IPC分类号： G06F17/50 , G06F17/10 , B60T17/22
CPC分类号： G06F17/5009 , B60T13/665 , B60T17/228 , G06F17/5095 , G06F2217/86
摘要： Disclosed is a brake HILS system for a railway vehicle, comprising: a user terminal that receives values relating to braking conditions of a railway vehicle through a user interface and monitors simulation results; a pneumatic brake that includes an electronic control unit, a brake operation unit, a wheelset, a brake caliper, and a wheel slide protection valve and produces pneumatic pressure and transmits a braking force to the wheelset in accordance with the braking conditions from the user terminal; a load cell that is disposed on a wheel or a disc and measures a braking force from the pneumatic pressure; and a modeling unit that simulates the running and braking dynamic characteristics of a railway vehicle in real-time using mathematical models.
摘要翻译：公开了一种用于铁路车辆的制动器HILS系统，包括：用户终端，通过用户接口接收与铁路车辆的制动条件相关的值，并监视模拟结果; 气动制动器，其包括电子控制单元，制动操作单元，轮对，制动钳和车轮滑动保护阀，并产生气动压力，并根据来自用户终端的制动条件向车轮传递制动力 ; 设置在车轮或盘上并由气动压力测量制动力的测力传感器; 以及使用数学模型实时模拟铁路车辆运行和制动动态特性的建模单元。

10. 发明授权

US09122826B1 Method and apparatus for performing compilation using multiple design flows 有权
标题翻译：使用多个设计流程进行编译的方法和装置
公开(公告)号：US09122826B1
公开(公告)日：2015-09-01
申请号：US14052210
申请日：2013-10-11
申请人： Altera Corporation
发明人： Terry Borer , Andrew Leaver , David Karchmer , Gabriel Quan , Stephen D. Brown
IPC分类号： G06F17/50 , G01R31/3183
CPC分类号： G06F17/5054 , G01R31/318364 , G06F17/5045 , G06F17/505 , G06F17/5072 , G06F2217/04 , G06F2217/86
摘要： A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.
摘要翻译：一种用于在目标设备上设计系统的方法包括将从自下而上的设计流程生成的系统的第一分区的网表与用于系统的第二分区的网表从上到下的设计流程合并，形成组合网表，并在组合网表上执行拟合。

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