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1. 发明申请

US20190243612A1 RANDOM BIT STREAM GENERATOR AND METHOD THEREOF 审中-公开
公开(公告)号：US20190243612A1
公开(公告)日：2019-08-08
申请号：US16159734
申请日：2018-10-15
申请人： Novatek Microelectronics Corp.
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang
IPC分类号： G06F7/58 , H03K3/84 , H03M3/00
CPC分类号： G06F7/584 , H03K3/84 , H03M3/414
摘要： A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

2. 发明申请

US20180225094A1 RANDOM NUMBER GENERATING DEVICE AND RANDOM NUMBER GENERATING METHOD 审中-公开
公开(公告)号：US20180225094A1
公开(公告)日：2018-08-09
申请号：US15835115
申请日：2017-12-07
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Masami Nakajima
IPC分类号： G06F7/58 , H01L23/522 , H01L23/31
CPC分类号： G06F7/584 , G06F7/588 , H01L23/3142 , H01L23/5226
摘要： To generate a random number with a larger number of bits and with reduced predictability, a random number generating device 1 includes a sensor 2 that measures a physical phenomenon, a seed value generator 3, and a random number generator 4. The seed value generator 3 generates a seed value for random number generation by using n bits (n is an integer from 1 to N) of an N-bit (N is an integer of 1 or more) digital value indicating a measured value of the sensor 2. The random number generator 4 generates an M-bit (M is an integer of more than n) random number by using the seed value generated by the seed value generator 3, with use of a predetermined pseudorandom number generation algorithm that generates a pseudorandom number with a larger number of bits than the number of bits of the seed value.

3. 发明申请

US20180101360A1 SECURED PSEUDO-RANDOM NUMBER GENERATOR 审中-公开
公开(公告)号：US20180101360A1
公开(公告)日：2018-04-12
申请号：US15289211
申请日：2016-10-10
申请人： International Business Machines Corporation
发明人： Yutaka Kawai , Yohichi Miwa
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F7/582
摘要： The present invention provides a method of generating a sequence of pseudo-random numbers which are difficult to predict. The method includes: (i) generating a plurality of candidate pseudo-random numbers by a respectively corresponding plurality of (differently structured) linear feedback shift registers; (ii) generating a “selector number” from one or more additional linear feedback shift registers; and (iii) selecting a candidate number from the plurality of candidate numbers, based on the “selection number” to produce a selected pseudo-random number for output.

4. 发明授权

US09875085B2 Memory system and method of generating a seed value 有权
公开(公告)号：US09875085B2
公开(公告)日：2018-01-23
申请号：US14811481
申请日：2015-07-28
申请人： SanDisk Technologies Inc.
发明人： Rishi Mukhopadhyay , Abhijeet Manohar , Rajesh Neermarga
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F7/584
摘要： A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

5. 发明申请

US20170230169A1 SECURE DATA STORAGE 审中-公开
公开(公告)号：US20170230169A1
公开(公告)日：2017-08-10
申请号：US15424842
申请日：2017-02-04
申请人： NXP B.V.
发明人： Sebastien Riou
IPC分类号： H04L9/00 , G06F21/72 , G06F7/58 , H04L9/06
CPC分类号： H04L9/004 , G06F7/584 , G06F7/588 , G06F21/72 , G06K19/073 , G06K19/07309 , G06K19/07318 , G06K19/07363 , G09C1/00 , G11C7/24 , G11C13/0059 , H04L9/003 , H04L9/0643 , H04L9/0894
摘要： The disclosure relates to secure data storage and retrieval, in particular to methods and circuits for securely storing data to reduce the possibility of leakage via side channel attacks. Embodiments disclosed include a method of storing a value comprising a series of words, the method comprising: i) combining in a series of XOR operations a word of a first portion of the value, a word of a second portion of the value and an output word of a first random number generator to provide a first combined word; ii) storing the first combined word in a shift register; and iii) repeating steps i) and ii) for each successive word of the first and second portions of the value.

6. 发明申请

US20170192830A1 HIGH-SPEED PSEUDO-RANDOM BIT SEQUENCE (PRBS) PATTERN GENERATOR, ERROR DETECTOR AND ERROR COUNTER 审中-公开
公开(公告)号：US20170192830A1
公开(公告)日：2017-07-06
申请号：US14986347
申请日：2015-12-31
申请人： Avago Technologies General IP (Singapore) Pte. Ltd
发明人： Dezhao Bai , Faouzi Chaahoub
IPC分类号： G06F11/07 , H03K3/84 , G06F7/58
CPC分类号： H03K3/84 , G06F7/584 , G06F2207/581
摘要： High-speed PRBS-N pattern generator, error detector and error counter circuits are provided that have relatively simple circuit configurations, that quickly synchronize and align the input data with the generated pattern, that easily and quickly detect the occurrence of a bit shifting event, and that quickly resynchronize and realign the input data with the generated pattern after a bit shifting event has occurred. The error counter may be implemented with low-speed circuitry even though the pattern generator and error detector operate at the same speed as the high-speed input data signal. This reduces the complexity and power consumption of the error counter.

7. 发明申请

US20160210226A1 METHOD AND APPARATUS FOR TESTING ELECTRONIC SYSTEM 有权
标题翻译：用于测试电子系统的方法和装置
公开(公告)号：US20160210226A1
公开(公告)日：2016-07-21
申请号：US14777916
申请日：2014-03-28
申请人： RANDOMIZE LIMITED
发明人： Giles Thomas Hall
IPC分类号： G06F11/36
CPC分类号： G06F11/3688 , G06F7/584 , G06F11/3672 , G06F11/3676 , G06F11/3684 , G06F11/3692
摘要： A verification apparatus and method are disclosed for testing a device or system which is operable in a number of states through which it can transition in a multiplicity of different sequences. The method and apparatus disclosed include a set of functional modules which correspond to the states of the device or system under test and which may be activated in a large number of pseudorandom sequences. Each time a module of the verification apparatus is activated it causes the device or system under test to transition to the corresponding state. Thus, when the functional modules of the verification apparatus are activated in a given sequence, the corresponding states of the device or system under test are called in the same sequence.
摘要翻译：公开了一种验证装置和方法，用于测试可在许多状态下操作的装置或系统，通过它们可以以多种不同的顺序转换。所公开的方法和装置包括一组功能模块，其对应于被测设备或系统的状态，并且可以在大量的伪随机序列中被激活。每次验证装置的模块被激活时，使被测设备或系统转变到相应的状态。因此，当以给定的顺序激活验证装置的功能模块时，以相同的顺序调用被测设备或被测系统的相应状态。

8. 发明授权

US09361214B2 System of generating scramble data and method of generating scramble data 有权
标题翻译：产生加扰数据的系统和产生加扰数据的方法
公开(公告)号：US09361214B2
公开(公告)日：2016-06-07
申请号：US13873260
申请日：2013-04-30
申请人： Etron Technology, Inc.
发明人： Wen-Min Lu
IPC分类号： G06F12/00 , G06F7/58 , G06F21/60 , G06F12/02
CPC分类号： G06F12/00 , G06F7/58 , G06F7/582 , G06F7/584 , G06F12/0246 , G06F21/60
摘要： A system of generating scramble data includes a linear feedback shift register and a scramble engine. The linear feedback shift register is used for generating a plurality of first scramble values according to an initial value. The scramble engine is coupled to the linear feedback shift register for utilizing at least one bit of a first scramble value of the plurality of first scramble values to execute a first logic operation on other bits of the first scramble value to generate a second scramble value corresponding to the first scramble value. A bit number of the second scramble value is the same as a bit number of the first scramble value.
摘要翻译：产生加扰数据的系统包括线性反馈移位寄存器和加扰引擎。线性反馈移位寄存器用于根据初始值产生多个第一扰频值。加扰引擎耦合到线性反馈移位寄存器，用于利用多个第一加扰值的第一加扰值的至少一个比特来对第一加扰值的其他比特执行第一逻辑运算以产生对应的第二加扰值到第一个争夺的价值。第二加扰值的位数与第一加扰值的位数相同。

9. 发明授权

US09298423B2 Methods and systems for determining characteristics of a sequence of n-state symbols 有权
标题翻译：用于确定n态符号序列的特征的方法和系统
公开(公告)号：US09298423B2
公开(公告)日：2016-03-29
申请号：US13831394
申请日：2013-03-14
申请人： Peter Lablans
发明人： Peter Lablans
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F7/58
摘要： Maximum length properties of n-state sequences of n-state symbols with n=2 or n>2 are tested. Checkwords are generated from p consecutive n-state symbols in a sequence of n-state symbols which may overlap by (p−1) n-state symbols. If a sequence has np−1 n-state symbols in which 2 consecutive checkwords overlap in (p−1) n-state symbols and each checkword formed in the extended sequence is unique, then the sequence is a maximum length n-state sequence. An n-state feedback shift register based sequence generator with p n-state register elements is tested on the content of the shift register for np−1 cycles. If the shift register content is not repeated the sequence is maximum length. Generation of a sequence is stopped when the content repeats. Non-reversible n-state inverters and non-reversible n-state logic functions are applied to generate n-state sequences.
摘要翻译：对具有n = 2或n> 2的n状态符号的n状态序列的最大长度特性进行测试。在n个状态符号的序列中，可以由（p-1）个n状态符号重叠的p个连续n状态符号生成检查词。如果序列具有np-1个n状态符号，其中2个连续检查词在（p-1）个n状态符号中重叠，并且在扩展序列中形成的每个复制词是唯一的，则该序列是最大长度n状态序列。根据np-1个周期的移位寄存器的内容测试具有p n状态寄存器元件的基于n状态反馈移位寄存器的序列发生器。如果移位寄存器的内容不重复，序列是最大长度。当内容重复时，停止生成序列。应用不可逆的n态反相器和非可逆n态逻辑函数来产生n态序列。

10. 发明授权

US09280317B2 Semiconductor memory device and random number generator 有权
标题翻译：半导体存储器件和随机数发生器
公开(公告)号：US09280317B2
公开(公告)日：2016-03-08
申请号：US13945186
申请日：2013-07-18
申请人： Kabushiki Kaisha Toshiba
发明人： Yosuke Kondo
IPC分类号： G06F7/58
CPC分类号： G06F7/584
摘要： According to one embodiment, semiconductor memory device and a random number generator includes A semiconductor memory device includes: a semiconductor memory 30, a random number generator 10 generating a random number sequence, and a data writing unit 20 storing data in the semiconductor memory 30 using the random number sequence. The random number generator 10 includes: a random number generating unit generating an M-bit random number sequence; a coefficient selecting unit outputs a first coefficient or a second coefficient to the random number generating unit; and a bit selecting unit which outputs the random number sequence obtained by selecting N bits from M-bit random number sequence output from the random number generating unit.
摘要翻译：根据一个实施例，半导体存储器件和随机数发生器包括：半导体存储器件，包括：半导体存储器30，产生随机数序列的随机数发生器10以及数据写入单元20，其使用随机数序列。随机数发生器10包括：产生M位随机数序列的随机数生成单元; 系数选择单元向随机数生成单元输出第一系数或第二系数; 以及位选择单元，其输出通过从随机数生成单元输出的M位随机数序列中选择N位而获得的随机数序列。

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