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1. 发明申请

US20180357064A1 STREAM PROCESSOR WITH HIGH BANDWIDTH AND LOW POWER VECTOR REGISTER FILE 审中-公开
公开(公告)号：US20180357064A1
公开(公告)日：2018-12-13
申请号：US15644045
申请日：2017-07-07
申请人： Advanced Micro Devices, Inc.
发明人： Jiasheng Chen , Bin He , Mark M. Leather , Michael J. Mantor , Yunxiao Zou
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0875 , G06F12/0891
CPC分类号： G06F9/3867 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/3012 , G06F9/30141 , G06F9/3802 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3857 , G06F12/0804 , G06F12/0855 , G06F12/0875 , G06F12/0891 , G06F12/121 , G06F2212/1008 , G06F2212/1024 , G06F2212/452
摘要： Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

2. 发明申请

US20180247185A1 HARDWARE NODE WITH POSITION-DEPENDENT MEMORIES FOR NEURAL NETWORK PROCESSING 审中-公开
公开(公告)号：US20180247185A1
公开(公告)日：2018-08-30
申请号：US15637426
申请日：2017-06-29
申请人： Microsoft Technology Licensing, LLC
发明人： Eric S. Chung , Douglas C. Burger , Jeremy Fowers
IPC分类号： G06N3/04 , G06F17/16 , G06F9/30 , G06F9/26
CPC分类号： G06F17/16 , G06F9/265 , G06F9/30036 , G06F9/30141 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06F9/3891 , G06N3/02 , G06N3/04 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N3/08 , H03K19/17796
摘要： Processors and methods for neural network processing are provided. A method in a processor including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the matrix vector unit, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes decoding a chain of instructions received via an input queue, where the chain of instructions comprises a first instruction that can only be processed by the matrix vector unit and a sequence of instructions that can only be processed by a multifunction unit. The method includes processing the first instruction using the MVU and processing each of instructions in the sequence of instructions depending upon a position of the each of instructions in the sequence of instructions.

3. 发明申请

US20180217840A1 AN APPARATUS AND METHOD FOR TRANSFERRING A PLURALITY OF DATA STRUCTURES BETWEEN MEMORY AND ONE OR MORE VECTORS OF DATA ELEMENTS STORED IN A REGISTER BANK 审中-公开
公开(公告)号：US20180217840A1
公开(公告)日：2018-08-02
申请号：US15746559
申请日：2016-06-15
申请人： ARM LIMITED
发明人： Mbou EYOLE , Matthias Lothar BOETTCHER
IPC分类号： G06F9/30 , G06F15/80 , G06F3/06
CPC分类号： G06F9/30098 , G06F3/0611 , G06F3/0647 , G06F3/0656 , G06F3/0683 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30141 , G06F9/30145 , G06F15/8061 , G06F15/8076
摘要： An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises N data elements. Multi-axial buffer circuitry is provided having an array of storage elements, where along a first axis the array is organised as N sets of storage elements, each set containing a plurality VL of storage elements, and where along a second axis the array is organised as groups of N storage elements, with each group containing a storage element from each of the N sets. Access control circuitry then stores the N data elements of a received data structure in one of the groups selected in dependence on the associated identifier. Responsive to an indication that all required data structures have been stored in the multi-axial buffer circuitry, second interface circuitry then outputs the data elements stored in one or more of the sets of storage elements as one or more corresponding vectors of data elements for storage in a register bank, each vector containing VL data elements. Such an approach can significantly increase the performance of handling such load operations, and give rise to potential energy savings.

4. 发明授权

US09959246B2 Vector processor configured to operate on variable length vectors using implicitly typed instructions 有权
公开(公告)号：US09959246B2
公开(公告)日：2018-05-01
申请号：US14728522
申请日：2015-06-02
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Vitaly Kalashnikov
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F15/80 , G06F17/14
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

5. 发明申请

US20180046458A1 ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF THE ARITHMETIC PROCESSING DEVICE 审中-公开
公开(公告)号：US20180046458A1
公开(公告)日：2018-02-15
申请号：US15651651
申请日：2017-07-17
申请人： FUJITSU LIMITED
发明人： Masahiro Kuramoto
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/3012 , G06F9/30141 , G06F9/3887 , G06F17/16 , G06N3/0454 , G06N3/063 , G06N3/08
摘要： A memory 11 stores therein first data and second data each of which has element data that forms a matrix. Arithmetic units 51 to 53 repeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory 11, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

6. 发明申请

US20170352393A1 EMULATED MULTIPORT MEMORY ELEMENT CIRCUITRY WITH EXCLUSIVE-OR BASED CONTROL CIRCUITRY 审中-公开
公开(公告)号：US20170352393A1
公开(公告)日：2017-12-07
申请号：US15174460
申请日：2016-06-06
申请人： Altera Corporation
发明人： Pohrong Rita Chu
IPC分类号： G11C8/12 , G06F9/30 , G06F5/00 , G11C8/00 , G11C8/16
CPC分类号： G11C8/12 , G06F5/00 , G06F9/30141 , G11C7/1075 , G11C8/00 , G11C8/16
摘要： Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

7. 发明申请

US20170329610A1 FLEXIBLE MICROPROCESSOR REGISTER FILE 审中-公开
公开(公告)号：US20170329610A1
公开(公告)日：2017-11-16
申请号：US15607680
申请日：2017-05-29
申请人： ZIILABS INC., LTD.
发明人： Jonathan Bloomfield , John Robson , Nicholas J.N. Murphy
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30134 , G06F9/30141
摘要： Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

8. 发明授权

US09632783B2 Operand conflict resolution for reduced port general purpose register 有权
公开(公告)号：US09632783B2
公开(公告)日：2017-04-25
申请号：US14505854
申请日：2014-10-03
申请人： QUALCOMM Incorporated
发明人： Yun Du , Hongjiang Shang , Haikun Zhu
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3012 , G06F9/30141 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3832 , G06F9/3885 , G06F9/3887
摘要： Techniques are described for determining whether execution of an instruction would require reading more values from a memory cell of a general purpose register (GPR) than a read port of the memory cell would allow. In such a case, the techniques may store, prior to execution of the instruction, one or more values from the memory cell in a separate conflict queue. During execution of the instruction to implement an operation defined by the instruction, one value that is an operand of the operation would be read from the memory cell and another value that is an operand of the operation other would be read from the conflict queue.

9. 发明申请

US20160253175A1 Register File Having a Plurality of Sub-Register Files 有权
标题翻译：具有多个子寄存器文件的寄存器文件
公开(公告)号：US20160253175A1
公开(公告)日：2016-09-01
申请号：US14842983
申请日：2015-09-02
申请人： Imagination Technologies Limited
发明人： Hugh Jackson
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/30141 , G06F9/3802 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F12/0875 , G06F2212/452
摘要： Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.
摘要翻译：注册文件用于已被分为多个子注册表文件的乱序处理器。寄存器文件还具有多个缓冲器，每个缓冲器都与一个子寄存器文件相关联。每个缓冲器接收并存储发往相关子寄存器文件的写入操作，该文件可以稍后发布到子寄存器文件。具体地，每个时钟周期确定缓冲器中是否存在至少一个尚未发送到相关联的子寄存器文件的写入操作。如果缓冲器中至少有一个写入操作尚未发送到相关联的子寄存器文件，则其中一个未发出的写入操作将发送到关联的子寄存器文件。每个子寄存器文件还可以具有仲裁逻辑单元，该仲裁逻辑单元通过优先化读取操作来解决希望在相同周期中访问相关联的子寄存器文件的读取和写入操作之间的冲突，除非冲突的写入指令已经达到提交时间。

10. 发明申请

US20160224514A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH REGISTER RENAMING 审中-公开
标题翻译：矢量处理器被配置为在具有寄存器恢复功能的可变长度矢量上运行
公开(公告)号：US20160224514A1
公开(公告)日：2016-08-04
申请号：US14719432
申请日：2015-05-22
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary J. Nacer , Arthur Joseph Hoane
IPC分类号： G06F15/80 , G06F9/30
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The number of architected vector registers in the vector register file differs from the number of physical vector registers in the vector register file.
摘要翻译：公开了一种计算机处理器。计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个矢量寄存器以保存不同数量的元件。向量寄存器文件中的架构向量寄存器数量与向量寄存器文件中物理向量寄存器的数量不同。

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