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1. 发明授权

US11775304B2 Methods and apparatus to insert profiling instructions into a graphics processing unit kernel 有权
公开(公告)号：US11775304B2
公开(公告)日：2023-10-03
申请号：US17359114
申请日：2021-06-25
申请人： Intel Corporation
发明人： Konstantin Levit-Gurevich , Orr Goldman
IPC分类号： G06F11/34 , G06T1/20 , G06F11/36 , G06F9/32
CPC分类号： G06F9/322 , G06F11/34 , G06F11/3466 , G06F11/3636 , G06T1/20
摘要： Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes instructions, and at least one processor to execute the instructions to determine whether a GPU supports modification of entry point addresses, detect a first entry point address and a second entry point address of an original GPU kernel, create a corresponding instrumented GPU kernel from the original GPU kernel based on the determination by inserting at least one of first profiling initialization instructions or first jump instructions at the first entry point address of the instrumented GPU kernel, inserting at least one of second profiling initialization instructions or second jump instructions at the second entry point address of the instrumented GPU kernel, and inserting profiling measurement instructions into the instrumented GPU kernel.

2. 发明申请

US20190079770A1 BRANCH INSTRUCTION 审中-公开
公开(公告)号：US20190079770A1
公开(公告)日：2019-03-14
申请号：US16085053
申请日：2017-03-21
申请人： ARM Limited
发明人： Thomas Christopher GROCUTT , Richard Roy GRISENTHWAITE , Simon John CRASKE , François Christopher Jacques BOTMAN , Bradley John SMITH
IPC分类号： G06F9/38 , G06F9/30 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/3005 , G06F9/30054 , G06F9/30145 , G06F9/321 , G06F9/322 , G06F9/34
摘要： A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.

3. 发明申请

US20190065196A1 REDUCED LOGIC LEVEL OPERATION FOLDING OF CONTEXT HISTORY IN A HISTORY REGISTER IN A PREDICTION SYSTEM FOR A PROCESSOR-BASED SYSTEM 审中-公开
公开(公告)号：US20190065196A1
公开(公告)日：2019-02-28
申请号：US15685519
申请日：2017-08-24
申请人： QUALCOMM Incorporated
发明人： Anil Krishna , Yongseok Yi , Vignyan Reddy Kothinti Naresh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/30149 , G06F9/322 , G06F9/3806 , G06F9/3844 , G06F9/3848 , G06F9/3861
摘要： Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction system includes a prediction circuit employing reduced operation folding of the history register for indexing a prediction table containing prediction values used to process a consumer instruction when value has not yet been resolved. To avoid the requirement to perform successive logic folding operations to produce a folded context history of a resultant reduced bit width, reduced logic level folding operation of the resultant reduced bit width is employed. Reduced logic level folding operation of the resultant reduced bit width involves using current folded context history from previous contents of a history register as basis for determining a new folded context history. In this manner, logic folding of the history register is faster and operates with reduced power consumption as a result of fewer logic operations.

4. 发明授权

US10055227B2 Using the least significant bits of a called function's address to switch processor modes 有权
公开(公告)号：US10055227B2
公开(公告)日：2018-08-21
申请号：US13655499
申请日：2012-10-19
申请人： QUALCOMM Incorporated
发明人： Charles Joseph Tabony , Erich James Plondke , Lucian Codrescu , Suresh K. Venkumahanti , Evandro Carlos Menezes
IPC分类号： G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/30189 , G06F9/30054 , G06F9/30076 , G06F9/30149 , G06F9/30181 , G06F9/322 , G06F9/3816
摘要： Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

5. 发明授权

US09959120B2 Persistent relocatable reset vector for processor 有权
公开(公告)号：US09959120B2
公开(公告)日：2018-05-01
申请号：US13750013
申请日：2013-01-25
申请人： Apple Inc.
发明人： Josh P. de Cesare , Gerard R. Williams, III , Michael J. Smith , Wei-Han Lien
IPC分类号： G06F1/32 , G06F9/32 , G06F9/30
CPC分类号： G06F9/322 , G06F9/30076
摘要： In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

6. 发明申请

US20180067745A1 ACCELERATED EXECUTION OF EXECUTE INSTRUCTION TARGET 审中-公开
公开(公告)号：US20180067745A1
公开(公告)日：2018-03-08
申请号：US15798887
申请日：2017-10-31
申请人： International Business Machines Corporation
发明人： Khary J. Alexander , Fadi Y. Busaba , Brian W. Curran , David S. Hutton , Edward T. Malley , Brian R. Prasky , John G. Rell, JR.
IPC分类号： G06F9/38 , G06F9/32 , G06F9/30
CPC分类号： G06F9/3822 , G06F9/30032 , G06F9/3005 , G06F9/30145 , G06F9/3016 , G06F9/30181 , G06F9/322 , G06F9/3867
摘要： As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

7. 发明申请

US20170068541A1 GUEST INSTRUCTION TO NATIVE INSTRUCTION RANGE BASED MAPPING USING A CONVERSION LOOK ASIDE BUFFER OF A PROCESSOR 审中-公开
标题翻译：使用转换视图处理器的缓冲区的指南到基于范围的映射
公开(公告)号：US20170068541A1
公开(公告)日：2017-03-09
申请号：US15354679
申请日：2016-11-17
申请人： Soft Machines, Inc.
发明人： Mohammad Abdallah
IPC分类号： G06F9/30 , G06F12/0875 , G06F9/38
CPC分类号： G06F9/30174 , G06F8/52 , G06F9/30058 , G06F9/322 , G06F9/3802 , G06F9/3808 , G06F12/0875 , G06F2212/151 , G06F2212/452
摘要： A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.
摘要翻译：一种用于翻译处理器的指令的方法。该方法包括：访问包含多个客户分支指令的多个访客指令，以及将多个访客指令组装成访客指令块。客户指令块被转换为相应的本机转换块。访客指令块到对应的本机转换块的映射被存储在转换后备缓冲器中。在对客户指令的后续请求之后，转换看起来缓冲器被索引以确定是否发生命中，其中该映射指示访客指令是否具有本地高速缓存中的对应转换的本机指令。转换的本地指令被转发以执行命令。

8. 发明申请

US20160321077A1 GUEST TO NATIVE BLOCK ADDRESS MAPPINGS AND MANAGEMENT OF NATIVE CODE STORAGE 审中-公开
标题翻译：对本地区地址映射的访问和本地代码存储的管理
公开(公告)号：US20160321077A1
公开(公告)日：2016-11-03
申请号：US15208404
申请日：2016-07-12
申请人： Soft Machines, Inc.
发明人： Mohammad Abdallah
IPC分类号： G06F9/355 , G06F12/0897 , G06F12/0895 , G06F9/38 , G06F9/30
CPC分类号： G06F9/355 , G06F9/30054 , G06F9/30174 , G06F9/322 , G06F9/3802 , G06F9/4552 , G06F12/0895 , G06F12/0897 , G06F12/1036 , G06F2212/604
摘要： A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.
摘要翻译：一种用于管理用于处理器的代码高速缓存上的存储的映射的方法。该方法包括将多个访客地址存储为本地地址映射作为转换看待缓冲区中的条目，其中条目指示具有存储在代码高速缓冲存储器中的相应转换的本机地址的访客地址，以及接收对访客地址的后续请求在转换看看缓冲区。将缓冲器的转换看起来被索引以确定是否存在对应于索引的条目，其中索引包括用于标识对应于索引的条目的标签和偏移。在标签上点击时，访问相应的条目以检索到转换的本地指令的代码高速缓冲存储器相应块的指针。转换的本地指令的相应块从代码高速缓冲存储器中取出以供执行。

9. 发明申请

US20160314071A1 COMPUTER PROCESSOR WITH REGISTER DIRECT BRANCHES AND EMPLOYING AN INSTRUCTION PRELOAD STRUCTURE 有权
标题翻译：具有注册直接分支机构的计算机处理器，并采用指令性预告结构
公开(公告)号：US20160314071A1
公开(公告)日：2016-10-27
申请号：US15087269
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
摘要： A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.
摘要翻译：公开了一种具有寄存器直接分支和采用指令预加载结构的计算机处理器。计算机处理器可以包括存储器层级，其包括以具有一个或多个对应于一个或多个指令的地址的一个或多个地址的一个或多个条目的结构组织的第一存储器。一个或多个地址的一个或多个条目可以具有起始地址。该结构可以具有用于存储一个或多个指令的一个或多个位置。计算机处理器可以包括一个或多个寄存器，一个或多个对应的指令地址可写入到该寄存器。计算机处理器可以包括处理逻辑。响应于将一个或多个指令地址写入一个或多个寄存器的处理逻辑，处理逻辑可以从存储器层级的第一存储器级别预先获取线性指令序列的一个或多个指令，从起始地址开始的存储器层级的第二存储器级别。一个或多个地址的至少一个地址可以是一个或多个寄存器的寄存器的内容。

10. 发明授权

US09459872B2 High-word facility for extending the number of general purpose registers available to instructions 有权
标题翻译：用于扩展可用于指令的通用寄存器数量的高位设备
公开(公告)号：US09459872B2
公开(公告)日：2016-10-04
申请号：US13726787
申请日：2012-12-26
申请人： International Business Machines Corporation
发明人： Dan F Greiner , Marcel Mitran , Timothy J Slegel
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30105 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/322 , G06F9/342
摘要： A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.
摘要翻译：计算机采用一组通用寄存器（GPR）。每个GPR包括多个部分。诸如操作系统和以大GPR模式运行的应用程序等程序可访问完整的GPR，但是以小GPR模式运行的应用程序等程序只能一次访问一部分。指令操作码，在小GPR模式下，可以确定访问哪个部分。

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