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1. 发明申请

US20190198752A1 MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR ENHANCEMENT LAYER 审中-公开
公开(公告)号：US20190198752A1
公开(公告)日：2019-06-27
申请号：US16287974
申请日：2019-02-27
申请人： Avalanche Technology, Inc.
发明人： Zihui Wang , Yiming Huai
IPC分类号： H01L43/08 , H01L29/66 , H01F10/32 , H01F41/30 , H01L27/22 , G11C11/15 , H01L43/10 , H01L43/02 , G11C11/16
CPC分类号： H01L43/08 , B82Y40/00 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L27/228 , H01L29/66984 , H01L43/02 , H01L43/10
摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure including one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a magnesium perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer structure has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.

2. 发明申请

US20180358545A1 Silicon Oxynitride Based Encapsulation Layer for Magnetic Tunnel Junctions 审中-公开
公开(公告)号：US20180358545A1
公开(公告)日：2018-12-13
申请号：US15619825
申请日：2017-06-12
申请人： Headway Technologies, Inc.
发明人： Vignesh Sundar , Yu-Jen Wang , Dongna Shen , Sahil Patel , Ru-Ying Tong
IPC分类号： H01L43/10 , H01L43/02 , H01L27/22 , H01L21/02 , G11C11/15 , G11C11/16
CPC分类号： H01L43/10 , C23C16/308 , C23C16/505 , G11C11/15 , G11C11/161 , H01L21/02126 , H01L21/02274 , H01L27/222 , H01L43/02 , H01L43/12
摘要： A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

3. 发明授权

US10079338B2 Magnetic memory element with perpendicular enhancement layer 有权
公开(公告)号：US10079338B2
公开(公告)日：2018-09-18
申请号：US15794983
申请日：2017-10-26
申请人： Avalanche Technology, Inc.
发明人： Yiming Huai , Huadong Gan , Bing K. Yen
IPC分类号： H01L43/08 , H01F10/32 , G11C11/16 , H01L29/66 , H01L43/10 , H01L27/22 , H01F41/30 , H01L43/02 , B82Y40/00
CPC分类号： H01L43/08 , B82Y40/00 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L27/228 , H01L29/66984 , H01L43/02 , H01L43/10
摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer structure has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.

4. 发明申请

US20180246147A1 CURRENT SENSING SYSTEM AND CURRENT SENSING METHOD 审中-公开
公开(公告)号：US20180246147A1
公开(公告)日：2018-08-30
申请号：US15676939
申请日：2017-08-14
申请人： Monolithic Power Systems, Inc.
发明人： Serge Reymond , Pavel Kejik
IPC分类号： G01R15/20 , G01R33/07 , G11C11/15 , H01L43/04 , H01L43/06
CPC分类号： G01R15/202 , G01R15/207 , G01R19/0092 , G01R33/075 , G11C11/15 , H01L43/04 , H01L43/065
摘要： A current sensing system uses a Hall effect device. A conductor carrying a target current is shaped in a way such that two regions with opposite magnetic field directions crossed there through are created at a silicon die which contains the Hall effect devices placed in a mirror way. The Hall effect devices react the magnetic field to generate a Hall voltage when a bias current is applied, which is then processed by a process circuit and an operational unit, so that a differential signal indicative of the target current is generated.

5. 发明申请

US20180166114A1 ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20180166114A1
公开(公告)日：2018-06-14
申请号：US15894737
申请日：2018-02-12
申请人： SK hynix Inc.
发明人： Jae-Yun Yi , Sung-Woong Chung , Seok-Pyo Song
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , H01L43/08
摘要： An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

6. 发明申请

US20170365361A1 SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME 审中-公开
公开(公告)号：US20170365361A1
公开(公告)日：2017-12-21
申请号：US15696794
申请日：2017-09-06
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Uhn CHA , Hoi-Ju CHUNG , Jong-Pil SON , Kwang-II PARK , Seong-Jin JANG
IPC分类号： G11C29/52 , G11C29/00 , G06F11/10 , G11C29/44 , G11C11/15 , G11C29/04
CPC分类号： G11C29/52 , G06F11/1048 , G11C11/15 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C29/702 , G11C2029/0411 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

7. 发明授权

US09734882B2 Magnetic memory cells with high write current and read stability 有权
公开(公告)号：US09734882B2
公开(公告)日：2017-08-15
申请号：US15012813
申请日：2016-02-01
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Vinayak Bharat Naik , Kiok Boone Elgin Quek
IPC分类号： H01L27/22 , H01L43/12 , H01L43/08 , G11C11/16 , H01L43/02 , G11C11/15
CPC分类号： G11C11/165 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/02
摘要： Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.

8. 发明申请

US20170125045A1 TERMINATION LAYER-COMPENSATED TUNNELING MAGNETORESISTANCE IN FERRIMAGNETIC HEUSLER COMPOUNDS WITH HIGH PERPENDICULAR MAGNETIC ANISOTROPY 有权
公开(公告)号：US20170125045A1
公开(公告)日：2017-05-04
申请号：US14925729
申请日：2015-10-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： SERGEY V. FALEEV , JAEWOO JEONG , STUART S.P. PARKIN , MAHESH G. SAMANT
IPC分类号： G11B5/39 , H01F10/32
CPC分类号： G11B5/3909 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/1936 , H01F10/3254 , H01F10/3286
摘要： A layered stack includes a first layer having a first spin polarization and a first magnetic moment, as well as a second layer (in contact with the first layer) having a second spin polarization a second magnetic moment. The first and second spin polarizations have the same orientation, but the first and second magnetic moments have orientations that partially cancel each other, thereby recommending the layered stack for applications in magnetic tunnel junctions, for example.

9. 发明授权

US09576635B2 Thermally-assisted magnetic writing device 有权
标题翻译：热辅助磁写装置
公开(公告)号：US09576635B2
公开(公告)日：2017-02-21
申请号：US14391570
申请日：2013-04-09
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Bernard Dieny
IPC分类号： G11C11/16 , G11C11/15 , G11C11/56 , G11C11/155
CPC分类号： G11C11/1675 , G11C11/15 , G11C11/155 , G11C11/161 , G11C11/1673 , G11C11/5607
摘要： A thermally-assisted magnetic writing device includes at least one magnetic element including: a reference layer having a stable vortex magnetization configuration; a device to create a magnetic field to reversibly move the vortex core in the plane of the reference layer; a storage layer having a variable magnetization configuration; a non-magnetic spacer that separates and magnetically decouples the reference layer and the storage layer; an antiferromagnetic pinning layer in contact with the storage layer, the antiferromagnetic layer being capable of pinning the magnetization configuration of the storage layer, the storage layer having at least two storage levels corresponding to two pinned magnetization configurations; a device to heat the antiferromagnetic pinning layer such that when heated, the temperature of the antiferromagnetic pinning layer exceeds its blocking temperature such that the magnetization configuration of the storage layer is no longer pinned when warm.
摘要翻译：热辅助磁性写入装置包括至少一个磁性元件，其包括：具有稳定的涡流磁化构型的参考层; 用于产生磁场以在所述参考层的平面中可逆地移动涡流核心的装置; 具有可变磁化结构的存储层; 分离和磁性去耦合参考层和存储层的非磁性间隔物; 与存储层接触的反铁磁钉扎层，所述反铁磁层能够固定所述存储层的磁化结构，所述存储层具有对应于两个钉扎磁化构型的至少两个存储电平; 用于加热反铁磁钉扎层的装置，使得当加热时，反铁磁性钉扎层的温度超过其阻挡温度，使得当温暖时存储层的磁化构型不再被固定。

10. 发明申请

US20170047107A1 METHOD AND APPARATUS FOR BIPOLAR MEMORY WRITE-VERIFY 审中-公开
标题翻译：双极存储器写入验证的方法和装置
公开(公告)号：US20170047107A1
公开(公告)日：2017-02-16
申请号：US15174482
申请日：2016-06-06
申请人： SPIN TRANSFER TECHNOLOGIES, INC.
发明人： Neal BERGER , Ben Louie , Mourad El-Baraji
IPC分类号： G11C11/16
CPC分类号： G11C11/1677 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.
摘要翻译：公开了一种用于双极存储器件的有利写入验证操作。在与写入操作相同的偏置条件下执行验证操作。因此，验证操作减少了在执行与验证操作相反的写入操作时产生的干扰条件。有利的写入验证操作可以用源和位线上的控制逻辑来执行。在另一个实施例中，利用耦合到控制逻辑的复用器来执行有利的写入操作。多路复用器确定是否应根据程序锁存器中的数据执行验证（0）或验证（1）操作。此外，多路复用器可以基于寄存器位选择用于读取操作的偏置条件。修剪电路可选地提供保护条带并修改参考电压，用于与正常读取操作相反极性执行的验证操作。

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