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1. 发明申请

US20180342305A1 STORAGE DEVICE AND METHOD OF OPERATING THE STORAGE DEVICE 审中-公开
公开(公告)号：US20180342305A1
公开(公告)日：2018-11-29
申请号：US15926419
申请日：2018-03-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SANG-SOO CHA , YOUNG-SEOP SHIM , DAE-WON KIM
IPC分类号： G11C16/34 , G11C16/26 , G06F13/16 , G06F13/40
CPC分类号： G11C16/3404 , G06F13/1673 , G06F13/4068 , G11C11/5642 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C16/26 , G11C16/3418 , G11C16/3436 , G11C16/3495 , G11C2013/0057
摘要： A method of operating a storage device includes: performing a background read operation on a nonvolatile memory by using a default read voltage level; performing a read retry operation on the nonvolatile memory by using a corrected read voltage level when the background read operation fails; storing the corrected read voltage level in a history buffer when the read retry operation succeeds; and performing a host read operation on the nonvolatile memory by using the history buffer in response to a read request received from a host.

2. 发明授权

US10074439B2 Modeling method of threshold voltage distributions 有权
公开(公告)号：US10074439B2
公开(公告)日：2018-09-11
申请号：US15174667
申请日：2016-06-06
申请人： SK hynix Inc.
发明人： Haibo Li , Shi Yin , Lingqi Zeng , Yu Cai , Fan Zhang , June Lee
IPC分类号： G11C16/04 , G11C16/34 , G11C7/02 , G11C11/56 , G11C16/10 , G11C29/04
CPC分类号： G11C16/3431 , G11C7/02 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3436 , G11C2029/0411
摘要： Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.

3. 发明申请

US20180075910A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20180075910A1
公开(公告)日：2018-03-15
申请号：US15606798
申请日：2017-05-26
申请人： SK hynix Inc.
发明人： Jin Yong SEONG
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34 , G11C16/26 , G11C16/30 , G11C16/08 , G11C16/24 , G11C11/34 , G11C11/063
CPC分类号： G11C16/10 , G06F13/16 , G11C7/1063 , G11C11/063 , G11C11/34 , G11C16/0483 , G11C16/08 , G11C16/22 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3436
摘要： Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.

4. 发明申请

US20180024948A1 BAD COLUMN MANAGEMENT WITH DATA SHUFFLE IN PIPELINE 审中-公开
公开(公告)号：US20180024948A1
公开(公告)日：2018-01-25
申请号：US15458561
申请日：2017-03-14
申请人： SANDISK TECHNOLOGIES LLC
发明人： Wanfang Tsai , Yan Li
IPC分类号： G06F13/16 , G06F5/06 , G11C16/34 , G06F3/06 , G11C16/04 , G11C16/10
CPC分类号： G06F13/1673 , G06F3/061 , G06F3/0655 , G06F3/0688 , G06F5/065 , G06F13/1642 , G06F2205/067 , G06F2212/2022 , G06F2212/7203 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3436 , G11C16/3454 , G11C29/84
摘要： Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

5. 发明授权

US09857992B2 Dynamic window to improve NAND endurance 有权
公开(公告)号：US09857992B2
公开(公告)日：2018-01-02
申请号：US15076963
申请日：2016-03-22
申请人： Intel Corporation
发明人： Kiran Pangal , Ravi J. Kumar
IPC分类号： G11C29/02 , G11C29/50 , G11C29/10 , G11C29/04 , G06F3/06 , G06F11/10 , G06F11/20 , G11C11/56 , G11C16/14 , G11C16/26 , G11C16/34 , G11C29/52 , G11C16/00
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/2094 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/14 , G11C16/26 , G11C16/3436 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0401
摘要： Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

6. 发明授权

US09620228B1 Monotonically increasing persistent counters 有权
公开(公告)号：US09620228B1
公开(公告)日：2017-04-11
申请号：US15078416
申请日：2016-03-23
申请人： Marvell International Ltd.
发明人： Amey Dattatray Inamdar
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16 , G11C16/04 , G11C16/105 , G11C16/3436
摘要： A monotonically increasing persistent counter is described that is persistent across reboots of a system in which it is incorporated. The described counter employs an event counter module that counts events that are generated by various event generators within the system. One type of event that can be counted by the described counter is a state change. In various implementations, the event counter module, when employed as a state change counter module, includes a state change counter that counts state changes, and a journal mode component which provides journaling functionality which makes it possible to accommodate large numbers of state changes while, at the same time, recover the counter in the event of a system failure. In at least some embodiments, one or both of the state change counter and the journal mode component are implemented using NOR flash memory.

7. 发明授权

US09570190B2 Semiconductor memory device to selectively perform a single sensing operation or a multi-sensing operation 有权
标题翻译：用于选择性地执行单个感测操作或多感测操作的半导体存储器件
公开(公告)号：US09570190B2
公开(公告)日：2017-02-14
申请号：US14716137
申请日：2015-05-19
申请人： SK hynix Inc.
发明人： Ka Young Cho
IPC分类号： G11C16/00 , G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C16/3436 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/3459
摘要： A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit configured to perform a program pulse applying operation and a verification operation on the memory cell array. The semiconductor memory device may include a control logic configured to control the peripheral circuit to selectively perform a single sensing operation or a multi sensing operation during the verification operation.
摘要翻译：提供一种半导体存储器件及其操作方法。半导体存储器件可以包括包括多个存储单元的存储单元阵列和被配置为对存储单元阵列执行编程脉冲施加操作和验证操作的外围电路。半导体存储器件可以包括配置成控制外围电路以在验证操作期间选择性地执行单个感测操作或多感测操作的控制逻辑。

8. 发明授权

US09535785B2 ECC method for flash memory 有权
标题翻译：闪存的ECC方法
公开(公告)号：US09535785B2
公开(公告)日：2017-01-03
申请号：US14158613
申请日：2014-01-17
申请人： Macronix International Co., Ltd.
发明人： Nai-Ping Kuo , Shih-Chang Huang , Chin-Hung Chang , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F11/10 , G11C16/34
CPC分类号： G06F11/1048 , G06F2212/1036 , G11C16/3436
摘要： A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
摘要翻译：提供了一种操作存储数据集的存储器和数据集的ECC的方法。如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

9. 发明申请

US20160357458A1 DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE 审中-公开
标题翻译：动态窗口提高NAND耐久性
公开(公告)号：US20160357458A1
公开(公告)日：2016-12-08
申请号：US15076963
申请日：2016-03-22
申请人： Intel Corporation
发明人： Kiran Pangal , Ravi J. Kumar
IPC分类号： G06F3/06 , G11C16/14 , G11C29/52 , G11C11/56 , G06F11/20 , G06F11/10 , G11C16/34 , G11C16/26
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/2094 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/14 , G11C16/26 , G11C16/3436 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0401
摘要： Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
摘要翻译：描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变计数值。或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化循环计数值。还公开并要求保护其他实施例。

10. 发明申请

US20160351263A1 APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS 有权
公开(公告)号：US20160351263A1
公开(公告)日：2016-12-01
申请号：US15170609
申请日：2016-06-01
申请人： Micron Technology, Inc.
发明人： Daniele Balluchi , Corrado Villa
IPC分类号： G11C16/10 , G11C13/00 , G11C16/34 , G11C16/26 , G11C16/08
CPC分类号： G11C16/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3436 , G11C16/3459 , G11C2213/79
摘要： The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

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