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1. 发明授权

US11705216B2 Data redirection upon failure of a program operation 有权
公开(公告)号：US11705216B2
公开(公告)日：2023-07-18
申请号：US17504778
申请日：2021-10-19
申请人： Micron Technology, Inc.
发明人： Adam J. Hieb
IPC分类号： G11C11/16 , G11C29/00 , G11C11/4093 , G06F13/16 , G06F3/06
CPC分类号： G11C29/848 , G06F3/0619 , G06F3/0646 , G06F3/0679 , G06F13/1673 , G11C11/4093
摘要： A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.

2. 发明授权

US09442675B2 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods 有权
标题翻译：在数据访问之前将数据从存储器中的有缺陷的数据条目重定向到冗余数据条目，以及相关的系统和方法
公开(公告)号：US09442675B2
公开(公告)日：2016-09-13
申请号：US14017760
申请日：2013-09-04
申请人： QUALCOMM Incorporated
发明人： Chiaming Chai , Shaoping Ge , Stephen Edward Liles
IPC分类号： G06F12/00 , G06F3/06 , G11C29/00
CPC分类号： G06F3/0689 , G06F3/0619 , G06F3/0665 , G11C29/785 , G11C29/848
摘要： Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.
摘要翻译：所公开的实施例包括在数据访问之前将数据从存储器中的缺陷数据条目重定向到冗余数据条目。还公开了相关系统和方法。存储器被配置为接收存储器访问请求。所接收的存储器访问请求包括数据输入地址。存储器使用数据输入地址来访问存储在第一数据访问路径中的存储器中的数据阵列中的数据。作为制造过程的结果，存储器中的行或列可能是有缺陷的。在数据阵列中的数据输入地址的行或列有缺陷的情况下，在数据访问之前，数据输入重定向电路将存储器访问请求重定向到数据阵列中的冗余行或列。

3. 发明授权

US09165681B2 Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block based on the actual location of the non-defective memory block 有权
标题翻译：对基于无缺陷存储器块的实际位置替换缺陷存储器块的无缺陷存储器块进行电压延迟校正
公开(公告)号：US09165681B2
公开(公告)日：2015-10-20
申请号：US14224543
申请日：2014-03-25
申请人： MICRON TECHNOLOGY, INC.
发明人： Vishal Sarin , Dzung H. Nguyen , William H. Radke
IPC分类号： G11C7/00 , G11C29/04 , G11C29/00
CPC分类号： G11C29/04 , G11C29/808 , G11C29/82 , G11C29/848
摘要： In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.
摘要翻译：在一个实施例中，有缺陷的存储器块被替换为非缺陷存储块，并且电压延迟校正被应用于基于无缺陷存储器的实际位置替换缺陷存储块的无缺陷存储器块块。

4. 发明申请

US20140321222A1 SEMICONDUCTOR MEMORY OF WHICH DEFECTIVE CELL IS REPLACEABLE WITH REDUNDANT CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY 审中-公开
标题翻译：有缺陷细胞的半导体存储器可以用冗余单元替代，半导体存储器的制造方法
公开(公告)号：US20140321222A1
公开(公告)日：2014-10-30
申请号：US14331401
申请日：2014-07-15
申请人： FUJITSU LIMITED
发明人： Yoshinori TOMITA , Hidetoshi MATSUOKA , Hiroyuki HIGUCHI
IPC分类号： G11C29/00 , H01L21/66
CPC分类号： G11C29/808 , G11C29/846 , G11C29/848 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.
摘要翻译：半导体存储器包括存储单元阵列，其包括x位的数据单元和用于每个字的y位的冗余单元; 位置数据存储单元，针对每个单词存储数据单元和冗余单元的缺陷单元的缺陷单元位置数据; 以及读取电路，其基于存储在所述位置数据存储单元中的针对指定为读取地址的指定字的所述位置数据存储单元中的缺陷单元位置数据从x位的单元读取数据，所述x位的单元由 x位的数据单元和除了有缺陷单元之外的指定字的y位的冗余单元。

5. 发明申请

US20140289569A1 SEMICONDUCTOR STORAGE DEVICE, CONTROLLER, AND MEMORY SYSTEM 审中-公开
标题翻译：半导体存储器件，控制器和存储器系统
公开(公告)号：US20140289569A1
公开(公告)日：2014-09-25
申请号：US14021068
申请日：2013-09-09
申请人： Kabushiki Kaisha Toshiba
发明人： Jota TACHIKAWA , Yasuyuki Matsuda
IPC分类号： G06F11/07
CPC分类号： G11C29/848 , G11C16/0483 , G11C29/4401 , G11C29/702 , G11C2029/0409 , G11C2229/743
摘要： According to one embodiment, a semiconductor storage device includes a memory cell array, a plurality of first latch circuits, a first register and a comparator. The memory cell array has a plurality of memory cells associated with columns. The first latch circuits are provided corresponding to the respective columns, and each of the first latch circuits holds data on whether or not the corresponding column has a failure. The first register holds the number of columns for redundancy. The comparator compares the number of the first latch circuits holding the data that the corresponding columns have failures with a criterion based on the data held by the first register. The semiconductor storage device determines whether or not there is a failure in the first latch circuit, based on the result of the comparison by the comparator.
摘要翻译：根据一个实施例，半导体存储装置包括存储单元阵列，多个第一锁存电路，第一寄存器和比较器。存储单元阵列具有与列关联的多个存储单元。第一锁存电路对应于相应的列设置，并且每个第一锁存电路保持关于相应的列是否有故障的数据。第一个寄存器保存冗余列数。比较器将基于第一寄存器保存的数据的相应列具有故障的数据的第一锁存电路的数量与标准进行比较。半导体存储装置基于比较器的比较结果来判定第一锁存电路是否存在故障。

6. 发明授权

US08842473B2 Techniques for accessing column selecting shift register with skipped entries in non-volatile memories 有权
标题翻译：用于访问列选择移位寄存器的技术，在非易失性存储器中跳过条目
公开(公告)号：US08842473B2
公开(公告)日：2014-09-23
申请号：US13420961
申请日：2012-03-15
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/02 , G11C16/06
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/848
摘要： Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.
摘要翻译：存在用于在循环移位寄存器中定位初始物理位置的技术，其中每个循环上都有随机跳过。这里，移位寄存器用于访问非易失性存储器中的列，其中跳过数组的有缺陷的列。查找表提供每个循环的初始跳过，提供从前一循环跳过的数量，以提供物理地址接近实际物理地址。移位寄存器的一种新结构可以在循环内实现自动移位模式。新结构具有一个额外的寄存器和逻辑门，用于计算当前指针之前跳过的条目数量，并相应地移动当前指针。

7. 发明申请

US20140269104A1 Sense Amplifier Column Redundancy 有权
标题翻译：感应放大器列冗余
公开(公告)号：US20140269104A1
公开(公告)日：2014-09-18
申请号：US13837874
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Chulmin Jung
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/28 , G11C29/702 , G11C29/848
摘要： A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense amplifier without requiring local read lines for each sense amplifier.
摘要翻译：存储器包括冗余读出放大器和多个读出放大器对。每个读出放大器对包括第一读出放大器和第二读出放大器。每个读出放大器对驱动公共负载线。存储器被配置为使用单个冗余读出放大器实现列冗余，而不需要每个读出放大器的本地读取线。

8. 发明授权

US08804395B2 Semiconductor device, control method thereof and data processing system 有权
公开(公告)号：US08804395B2
公开(公告)日：2014-08-12
申请号：US14147692
申请日：2014-01-06
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C5/06 , G11C29/00 , G11C5/02
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

9. 发明授权

US08670284B2 Semiconductor device, control method thereof and data processing system 失效
标题翻译：半导体器件，其控制方法和数据处理系统
公开(公告)号：US08670284B2
公开(公告)日：2014-03-11
申请号：US13431654
申请日：2012-03-27
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C7/00
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
摘要翻译：本文公开了一种半导体器件，其包括全局位线，耦合到正常存储器单元的第一本地位线，耦合到冗余存储器单元的第二局部位线和第二分层开关，对全局位线预充电的预充电电路，冗余确定所访问的地址是否匹配缺陷地址的确定电路以及控制电路。在待机状态下，全局位线和第二局部位线通过第二分层开关进行预充电。在激活状态下，第一本地位线通过第一分层交换机预先充电，随后当冗余确定电路确定地址不匹配时，第二分层交换机被停用以访问正常存储器单元，并且当冗余确定电路确定地址彼此匹配，第一分层交换机被停用以访问冗余存储器单元。

10. 发明申请

US20130148451A1 MEMORY DEVICE INCLUDING REDUNDANT MEMORY CELL BLOCK 有权
标题翻译：存储器件，包括冗余存储器单元块
公开(公告)号：US20130148451A1
公开(公告)日：2013-06-13
申请号：US13620280
申请日：2012-09-14
申请人： Tatsuru MATSUO
发明人： Tatsuru MATSUO
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C2029/4402
摘要： A clock signal is supplied to a first repair flag flip-flop, a second repair flag flip-flop, a first repair data flip-flop group, and a second repair data flip-flop group to serially transfer a second repair flag and a first repair flag stored in a non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop. Subsequently, repair data stored in the non-volatile memory is serially output to the first repair data flip-flop group, and repair data of the first repair data flip-flop group and the second repair data flip-flop group is serially transferred.
摘要翻译：时钟信号被提供给第一修复标志触发器，第二修复标志触发器，第一修复数据触发器组和第二修复数据触发器组，以串行地传送第二修复标志和第一修复标志存储在非易失性存储器中的第二修复标志触发器和第一修复标志触发器的修复标志。随后，存储在非易失性存储器中的修复数据被串行地输出到第一修复数据触发器组，并且第一修复数据触发器组和第二修复数据触发器组的修复数据被顺序传送。

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