专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190206718A1 BACK-END-OF-LINE STRUCTURES WITH AIR GAPS 审中-公开
公开(公告)号：US20190206718A1
公开(公告)日：2019-07-04
申请号：US15860121
申请日：2018-01-02
申请人： GLOBALFOUNDRIES Inc.
发明人： Nicholas V. LiCausi , Shao Beng Law , Sunil K. Singh , Xunyuan Zhang
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L21/311 , H01L21/3105 , H01L21/02
CPC分类号： H01L21/7682 , H01L21/02118 , H01L21/02274 , H01L21/31058 , H01L21/31111 , H01L21/76816 , H01L21/76828 , H01L23/528 , H01L23/53295 , H01L2221/1047
摘要： Interconnect structures and methods for forming an interconnect structure. First and second metallization structures are formed in an intralayer dielectric layer. The intralayer dielectric layer is removed to form a cavity with an entrance between the first and second metallization structures. A dielectric layer is deposited on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure. A sacrificial material is formed inside the cavity after the dielectric layer is deposited. A cap layer is deposited on the dielectric layer over the first metallization structure, the dielectric layer over the second metallization structure, and the sacrificial material inside the cavity to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer cooperate to encapsulate an air gap inside the cavity.

2. 发明申请

US20180374923A1 Semiconductor Structure and Manufacturing Method Thereof 审中-公开
公开(公告)号：US20180374923A1
公开(公告)日：2018-12-27
申请号：US16050747
申请日：2018-07-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L29/417 , H01L21/768 , H01L23/535 , H01L29/06 , H01L21/311 , H01L29/78
CPC分类号： H01L29/41775 , H01L21/31111 , H01L21/7682 , H01L21/76897 , H01L23/535 , H01L29/0653 , H01L29/41783 , H01L29/41791 , H01L29/7831 , H01L2221/1042 , H01L2221/1047 , H01L2221/1063
摘要： A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

3. 发明授权

US09666478B2 Methods of forming wiring structures and methods of manufacturing semiconductor devices 有权
公开(公告)号：US09666478B2
公开(公告)日：2017-05-30
申请号：US15048993
申请日：2016-02-19
申请人： Thomas Oszinda , Tae-Jin Yim , Sang-Hoon Ahn , Nae-In Lee
发明人： Thomas Oszinda , Tae-Jin Yim , Sang-Hoon Ahn , Nae-In Lee
IPC分类号： H01L21/76 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/3105 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L23/53238 , H01L23/5329 , H01L2221/1047
摘要： In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

4. 发明授权

US09583383B2 Air gap forming techniques based on anodic alumina for interconnect structures 有权
标题翻译：用于互连结构的基于阳极氧化铝的气隙形成技术
公开(公告)号：US09583383B2
公开(公告)日：2017-02-28
申请号：US15224728
申请日：2016-08-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Tien Wu , Tien-Lu Lin
IPC分类号： H01L23/48 , H01L23/50 , H01L29/40 , H01L21/768 , H01L21/02 , H01L23/532 , H01L23/528
CPC分类号： H01L21/7682 , H01L21/02178 , H01L21/02258 , H01L21/76807 , H01L21/76822 , H01L21/76826 , H01L21/76829 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L23/5222 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.
摘要翻译：在半导体衬底上形成铝（Al）层。去除Al层的选择性部分以形成开口。将Al层进行阳极氧化，得到具有多个孔的氧化铝介电层。开口填充有导电互连材料。孔被加宽以形成气隙，并且在氧化铝介质层上形成顶部蚀刻停止层。

5. 发明授权

US09564383B2 Low-K dielectric layer and porogen 有权
标题翻译：低K电介质层和致孔剂
公开(公告)号：US09564383B2
公开(公告)日：2017-02-07
申请号：US14733573
申请日：2015-06-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Joung-Wei Liou , Hui-Chun Yang , Yu-Yun Peng , Keng-Chu Lin
IPC分类号： H01L23/48 , H01L23/31 , H01L23/532 , H01L21/768 , H01L21/02
CPC分类号： H01L21/76879 , H01L21/02123 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/02321 , H01L21/76801 , H01L21/7682 , H01L21/76829 , H01L23/31 , H01L23/481 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
摘要翻译：提供了一种用于低k电介质层的系统和方法。优选的实施方案包括形成基质并在基质内形成致孔剂。致孔剂包括具有少于15个碳原子和大量单键的有机环结构。此外，致孔剂可能具有大于1.3的粘度和小于0.5的雷诺数。

6. 发明申请

US20160379874A1 Porogen Bonded Gap Filling Material in Semiconductor Manufacturing 有权
标题翻译：半导体制造中的致孔剂保温间隙填充材料
公开(公告)号：US20160379874A1
公开(公告)日：2016-12-29
申请号：US14752097
申请日：2015-06-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Bo-Jiun Lin , Ching-Yu Chang , Hai-Ching Chen , Tien-I Bao
IPC分类号： H01L21/768 , H01L23/532 , H01L21/02
CPC分类号： H01L21/76837 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/7682 , H01L23/5329 , H01L2221/1047
摘要： A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.
摘要翻译：一种用于半导体制造的方法，包括接收包括衬底和设置在衬底上的第一层的器件，其中第一层包括沟槽。所述方法还包括在所述第一层上施加第一材料并填充所述沟槽，其中所述第一材料包含与所述基质化学键合的基质和致孔剂。该方法还包括固化第一材料以形成多孔材料层。多孔材料层具有第一部分和第二部分。第一部分设置在沟槽中。第二部分设置在第一层上。第一和第二部分含有基本相同的Si，O和C的百分比。第一和第二部分含有基本相同的孔隙率。

7. 发明授权

US09362162B2 Methods of fabricating BEOL interlayer structures 有权
标题翻译：制作BEOL夹层结构的方法
公开(公告)号：US09362162B2
公开(公告)日：2016-06-07
申请号：US14459444
申请日：2014-08-14
申请人： GLOBALFOUNDRIES Inc.
发明人： Sunil Kumar Singh , Ravi Prakash Srivastava , Teck Jung Tang , Mark Alexander Zaleski
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76814 , H01L21/3105 , H01L21/31144 , H01L21/76807 , H01L21/7682 , H01L21/76825 , H01L2221/1047
摘要： Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).
摘要翻译：提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及施加减小一个开口的纵横比的能量。在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

8. 发明授权

US09312167B1 Air-gap structure formation with ultra low-k dielectric layer on PECVD low-k chamber 有权
标题翻译：在PECVD低k室上，采用超低k电介质层形成气隙结构
公开(公告)号：US09312167B1
公开(公告)日：2016-04-12
申请号：US14505731
申请日：2014-10-03
申请人： Applied Materials, Inc.
发明人： Taewan Kim , Kang Sub Yim , Alexandros T. Demos
IPC分类号： H01L21/76 , H01L21/764 , H01L21/02 , H01L29/06
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/02126 , H01L21/02312 , H01L21/7682 , H01L21/76885 , H01L2221/1047
摘要： Methods for reducing the k value of a layer using air gaps and devices produced by said methods are disclosed herein. Methods disclosed herein can include depositing a carbon containing stack over one or more features in a substrate, depositing a porous dielectric layer over the carbon containing stack, and curing the substrate to volatilize the carbon containing stack. The resulting device includes a substrate with one or more features formed therein, a porous dielectric layer formed over the features with an air gap formed in the features.
摘要翻译：本文公开了使用气隙降低层的k值的方法和由所述方法制造的装置。本文公开的方法可以包括在衬底中的一个或多个特征上沉积含碳堆叠，在含碳堆叠之上沉积多孔介电层，以及固化衬底以使含碳堆叠挥发。所得到的器件包括其中形成有一个或多个特征的衬底，在特征上形成的多孔介电层，其中形成有特征中的气隙。

9. 发明申请

US20160013050A1 INTEGRATED CIRCUITS WITH AN INSULTATING LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS 有权
标题翻译：具有绝缘层的集成电路和用于生产这种集成电路的方法
公开(公告)号：US20160013050A1
公开(公告)日：2016-01-14
申请号：US14325500
申请日：2014-07-08
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Ronny Pfutzner , Andreia Ioana Popa , Christof Streck
IPC分类号： H01L21/02 , H01L23/532 , H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L21/02318 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02323 , H01L21/02337 , H01L21/3105 , H01L21/76802 , H01L21/7682 , H01L21/76826 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for producing the same are provided. A method of producing the integrated circuits includes forming an insulating layer overlying a substrate. The insulating layer includes a first composition that includes silicon oxide and a porogen. The porogen is removed from the first composition to form a second composition that includes a pore, where the second composition has a dielectric constant lower than that of the first composition. An insulating layer mechanical property desired range is determined, where the second composition has an insulating material mechanical property outside of the insulating layer mechanical property desired range. The second composition is altered to form a third composition, where the third composition has the insulating layer mechanical property within the insulating layer mechanical property desired range.
摘要翻译：提供了集成电路及其制造方法。制造集成电路的方法包括形成覆盖在基板上的绝缘层。绝缘层包括包含氧化硅和致孔剂的第一组合物。造孔剂从第一组合物中除去以形成包含孔的第二组合物，其中第二组合物的介电常数低于第一组合物的介电常数。确定绝缘层机械性能期望范围，其中第二组合物具有在绝缘层机械性能期望范围之外的绝缘材料机械性能。改变第二组合物以形成第三组合物，其中第三组合物在绝缘层机械性能期望范围内具有绝缘层机械性能。

10. 发明申请

US20150311157A1 NANOTUBE STRUCTURE BASED METAL DAMASCENE PROCESS 审中-公开
标题翻译：基于纳米结构的金属吸附工艺
公开(公告)号：US20150311157A1
公开(公告)日：2015-10-29
申请号：US14738967
申请日：2015-06-15
申请人： Infineon Technologies AG
发明人： Ravi Joshi , Juergen Steinbrenner
IPC分类号： H01L23/532 , H01L21/311 , H01L21/285 , H01L21/02 , H01L23/528 , H01L21/768
CPC分类号： H01L23/528 , H01L21/02115 , H01L21/02527 , H01L21/02606 , H01L21/02645 , H01L21/28568 , H01L21/31138 , H01L21/76801 , H01L21/7682 , H01L21/76829 , H01L21/76871 , H01L21/76877 , H01L21/76885 , H01L23/53209 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.
摘要翻译：在各种实施例中，提供了一种用于在衬底上制造金属化层的方法，其中所述方法可以包括在衬底上形成多组纳米管，其中所述纳米管组可以被布置成使得衬底的一部分被暴露，在多组纳米管之间的衬底的暴露部分上形成金属。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式