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1. 发明公开

US20230369142A1 SEMICONDUCTOR DEVICE AND METHOD FOR DETERMINING DETERIORATION OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20230369142A1
公开(公告)日：2023-11-16
申请号：US18181171
申请日：2023-03-09
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motohito HORI , Yoshinari IKEDA , Takaaki TANAKA , Qichen WANG
IPC分类号： H01L21/66 , H01L23/049 , H01L23/373 , H01L23/00 , H01L25/18 , H01L25/07 , G01R31/28
CPC分类号： H01L22/32 , G01R31/2851 , H01L23/049 , H01L23/3735 , H01L24/48 , H01L25/072 , H01L25/18 , H01L2224/48139 , H01L2924/12031 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091
摘要： A semiconductor device includes a first input conductive plate on which a plurality of first semiconductor chips arranged in a first direction, a first output conductive plate extending in the first direction and being provided adjacent to the first input conductive plate, a case having first to fourth side walls for accommodating the first input conductive plate and the first output conductive plate, first main current wiring members, each of which connects one of the first output electrodes to a front surface of the first output conductive plate, a first detection terminal disposed in the first side wall, and a first detection wiring member connecting the front surface of the first output conductive plate to the first detection terminal. The first output conductive plate is disposed closer to the first side wall than is the first input conductive plate.

2. 发明公开

US20230197539A1 INTERPOSER CHIPS AND ENCLOSURES FOR QUANTUM CIRCUITS 审中-公开
公开(公告)号：US20230197539A1
公开(公告)日：2023-06-22
申请号：US17644695
申请日：2021-12-16
申请人： International Business Machines Corporation
发明人： David Abraham , John Michael Cotte
IPC分类号： H01L23/049 , H01L23/498 , H01L23/16 , H01L23/13 , H01L23/06 , H01L23/552 , H01L21/52
CPC分类号： H01L23/049 , H01L23/49888 , H01L23/16 , H01L23/13 , H01L23/06 , H01L23/552 , H01L21/52
摘要： Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.

3. 发明申请

US20180358949A1 ELECTRONIC COMPONENT HOUSING PACKAGE, ELECTRONIC APPARATUS, AND ELECTRONIC MODULE 审中-公开
公开(公告)号：US20180358949A1
公开(公告)日：2018-12-13
申请号：US15570900
申请日：2016-11-17
申请人： KYOCERA Corporation
发明人： Takuo KISAKI , Masaki SUZUKI
IPC分类号： H03H9/02 , H01L23/552 , H01L23/498 , H01L23/528 , H03H9/05 , H03H9/10 , H03H9/19
CPC分类号： H03H9/02086 , H01L23/02 , H01L23/04 , H01L23/049 , H01L23/13 , H01L23/49805 , H01L23/49822 , H01L23/49838 , H01L23/5286 , H01L23/552 , H01L2924/16195 , H03H9/02102 , H03H9/02133 , H03H9/0509 , H03H9/1021 , H03H9/1071 , H03H9/19
摘要： An electronic component housing package includes a base having a first principal face provided with a mounting section for mounting an electronic component; a frame having a second principal face, the frame being disposed on the base so as to surround the mounting section; a frame-shaped metallized layer disposed on the second principal face of the frame; and a side-surface conductor disposed on an inner side surface of the frame, the side-surface conductor connecting the frame-shaped metallized layer and a relay conductor formed on the first principal face, the side-surface conductor being covered with an insulating film from one end to the other end in a width direction of the side-surface conductor.

4. 发明申请

US20180315721A1 RADIO FREQUENCY CIRCUIT, WIRELESS COMMUNICATION DEVICE, AND METHOD OF MANUFACTURING RADIO FREQUENCY CIRCUIT 审中-公开
公开(公告)号：US20180315721A1
公开(公告)日：2018-11-01
申请号：US15945778
申请日：2018-04-05
申请人： FUJITSU LIMITED
发明人： Masaru Sato , Yukiyasu Furukawa
IPC分类号： H01L23/66 , H01L23/049 , H01L23/492 , H01L23/498 , H01L21/48 , H01L25/065 , H01L25/00 , H01Q1/22 , H01Q1/48
CPC分类号： H01L23/66 , H01L21/4817 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4875 , H01L23/04 , H01L23/041 , H01L23/043 , H01L23/049 , H01L23/055 , H01L23/492 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L25/0657 , H01L25/50 , H01L2223/6611 , H01L2223/6616 , H01L2223/6677 , H01L2223/6683 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06548 , H01L2225/06572 , H01L2924/15192 , H01L2924/16195 , H01Q1/2283 , H01Q1/48 , H01L2924/00014
摘要： A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.

5. 发明授权

US09812431B2 Power semiconductor module 有权
公开(公告)号：US09812431B2
公开(公告)日：2017-11-07
申请号：US14672467
申请日：2015-03-30
申请人： Fuji Electric Co., Ltd.
发明人： Tetsuya Inaba , Yoshinari Ikeda
IPC分类号： H01L25/07 , H01L23/049 , H01L23/492 , H01L23/498 , H01L23/24 , H01L23/373
CPC分类号： H01L25/072 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/492 , H01L23/49811 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A power semiconductor module is equipped with: a metal base; semiconductor chips electrically connected with and fixed to the metal base; and an insulating substrate fixed to the metal base and having a circuit plate on one surface. Additionally, the power semiconductor module is further equipped with a circuit board that is provided so as to face the semiconductor chips and the insulating substrate and that electrically connects electrodes of the semiconductor chips and the circuit plate of the insulating substrate. Further, the power semiconductor module is equipped with a conductive post that is electrically connected to at least one of either the electrodes of the semiconductor chips or the circuit plate of the insulating substrate while being electrically connected to the metal film of the circuit board.

6. 发明授权

US09698125B2 Power module with a plurality of patterns with convex and concave side 有权
公开(公告)号：US09698125B2
公开(公告)日：2017-07-04
申请号：US14863837
申请日：2015-09-24
申请人： Renesas Electronics Corporation
发明人： Yukihiro Sato , Katsuhiko Funatsu , Takamitsu Kanazawa , Masahiro Koido , Hiroyoshi Taya
IPC分类号： H01L23/48 , H01L21/44 , H01L25/065 , H01L23/498 , H01L25/07 , H01L23/00 , H01L23/049 , H01L21/48 , H01L23/373 , H01L25/16 , H01L25/18 , H02M7/219 , H01L23/24
CPC分类号： H01L25/0655 , H01L21/4846 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L23/49844 , H01L23/49861 , H01L24/09 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/16 , H01L25/18 , H01L2224/0603 , H01L2224/0905 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/13055 , H01L2924/13091 , H01L2924/16151 , H01L2924/16251 , H01L2924/181 , H02M7/219 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

7. 发明申请

US20160307817A1 POWER SEMICONDUCTOR MODULE 有权
标题翻译：功率半导体模块
公开(公告)号：US20160307817A1
公开(公告)日：2016-10-20
申请号：US15010114
申请日：2016-01-29
申请人： Mitsubishi Electric Corporation
发明人： Yoshitaka KIMURA , Rei YONEYAMA , Ryo GOTO , Akihiko YAMASHITA
IPC分类号： H01L23/367 , H01L23/40 , H01L23/492 , H01L23/049
CPC分类号： H01L23/049 , H01L23/10 , H01L23/36 , H01L23/3735 , H01L2224/48139
摘要： It is an object to provide a power semiconductor module having a case shared for base plates of different sizes and having a high-stability base plate. The power semiconductor module according to the present invention includes: a base plate; an insulating substrate disposed on a first main surface of the base plate; a semiconductor chip disposed on an insulating substrate; a case for enclosing the base plate except a second main surface of the base plate facing the first main surface, the insulating substrate, and the semiconductor chip; and a spacer provided between the outer periphery of the base plate and the inner periphery of the case and in contact with both. The spacer has a bonding surface with a side surface of the base plate and the first main surface in the contact with the outer periphery of the base plate.
摘要翻译：本发明的目的是提供一种功率半导体模块，其具有用于不同尺寸的基板共享的壳体，并且具有高稳定性基板。根据本发明的功率半导体模块包括：基板; 绝缘基板，设置在所述基板的第一主表面上; 设置在绝缘基板上的半导体芯片; 绝缘基板和半导体芯片的除基板的第二主面以外的基板的壳体; 以及设置在基板的外周与壳体的内周面并与两者接触的间隔件。间隔件具有与基板的侧表面和与基板的外周接触的第一主表面的接合表面。

8. 发明申请

US20160288259A1 LASER WELDING METHOD 审中-公开
标题翻译：激光焊接方法
公开(公告)号：US20160288259A1
公开(公告)日：2016-10-06
申请号：US15181988
申请日：2016-06-14
申请人： FUJI ELECTRIC CO., LTD.
发明人： Yuta TAMAI
IPC分类号： B23K26/20 , B23K26/00
CPC分类号： B23K26/206 , B23K26/0006 , B23K26/037 , B23K26/0622 , B23K26/211 , B23K26/22 , B23K26/32 , B23K2101/34 , B23K2101/35 , B23K2101/42 , B23K2103/08 , B23K2103/10 , B23K2103/12 , B23K2103/16 , B23K2103/172 , B23K2103/50 , H01L21/4846 , H01L23/049 , H01L23/3735 , H01L24/00 , H01L24/32 , H01L24/75 , H01L24/83 , H01L2224/32225 , H01L2224/32245 , H01L2224/37147 , H01L2224/3754 , H01L2224/40137 , H01L2224/75261 , H01L2224/7555 , H01L2224/83224 , H01L2224/83801 , H01L2224/83895 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079 , H01L2924/12042 , H01L2924/13055 , H01L2924/181 , H01L2924/19107 , H01L2924/40102 , H01L2924/00 , H01L2924/00012
摘要： A laser welding method using a laser welding jig having a plurality of pressing parts, includes a step of placing a second member on a first member; a step of pressing the second member with the plurality of pressing parts in a direction toward the first member to thereby form a gap between the first member and the second member at most 300 μm; and a first welding step of laser-welding the first member and the second member by irradiating on a surface of the second member at a location between the pressing parts with laser light while conducting the step of pressing.
摘要翻译：使用具有多个按压部件的激光焊接夹具的激光焊接方法包括将第二部件配置在第一部件上的工序; 在朝向第一部件的方向上按压多个按压部件的第二部件的步骤，从而在第一部件和第二部件之间形成最多300μm的间隙; 以及第一焊接步骤，通过在进行压制步骤的同时用激光在所述按压部件之间的位置处照射所述第二部件的表面来激光焊接所述第一部件和所述第二部件。

9. 发明申请

US20160254203A1 Semiconductor Package Having a Multi-Layered Base 有权
标题翻译：具有多层基底的半导体封装
公开(公告)号：US20160254203A1
公开(公告)日：2016-09-01
申请号：US14948072
申请日：2015-11-20
申请人： Infineon Technologies Americas Corp.
发明人： Shunhe Xiong , Grant Maloney
IPC分类号： H01L23/043 , H05K1/18 , H01L23/498 , H01L23/08 , H01L23/373
CPC分类号： H01L23/043 , H01L23/049 , H01L23/08 , H01L23/373 , H01L23/4952 , H01L23/49555 , H01L23/49562 , H01L23/49844 , H01L23/49866 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04026 , H01L2224/04042 , H01L2224/06181 , H01L2224/291 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/10253 , H01L2924/1027 , H01L2924/10272 , H01L2924/1032 , H01L2924/1033 , H01L2924/10344 , H01L2924/16195 , H01L2924/181 , H05K1/181 , H05K2201/068 , Y02P70/611 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the semiconductor die at a top surface of the conductive base, where the conductive base includes a first layer having a first coefficient of thermal expansion (CTE), and a second layer having at least one mounting tab and a second CTE. The conductive base is configured to reduce thermal stress in the ceramic case, where the first CTE is equal to or slightly different than a CTE of the ceramic case, the second CTE is greater than the first CTE, and a CTE of the PCB is greater than or equal to the second CTE. The conductive base is configured to electrically couple a power electrode of the semiconductor die to the PCB.
摘要翻译：用于安装到印刷电路板（PCB）的半导体封装包括在陶瓷壳体中的半导体管芯，在导电基底的顶表面处耦合到半导体管芯的导电基底，其中导电基底包括具有第一热膨胀系数（CTE），以及具有至少一个安装片和第二CTE的第二层。导电基底被配置为降低陶瓷壳体中的热应力，其中第一CTE等于或稍微不同于陶瓷壳体的CTE，第二CTE大于第一CTE，并且PCB的CTE更大超过或等于第二CTE。导电基座被配置为将半导体管芯的功率电极电耦合到PCB。

10. 发明申请

US20160240452A1 SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS 审中-公开
标题翻译：具有子端子的半导体封装及相关方法
公开(公告)号：US20160240452A1
公开(公告)日：2016-08-18
申请号：US14624893
申请日：2015-02-18
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Atapol Prajuckamol , Chee Hiong Chew , Azhar Aripin
IPC分类号： H01L23/31 , H01L23/08 , H01L21/56 , H01L21/78 , H01L21/52 , H01L23/04 , H01L23/498
CPC分类号： H01L21/78 , H01L21/54 , H01L23/049 , H01L23/24 , H01L23/49811 , H01L24/06 , H01L24/16 , H01L24/32 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/0655 , H01L25/072 , H01L2224/0401 , H01L2224/04034 , H01L2224/04042 , H01L2224/06181 , H01L2224/16227 , H01L2224/32225 , H01L2224/40137 , H01L2224/40227 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48472 , H01L2224/73263 , H01L2224/73265 , H01L2224/84 , H01L2224/92246 , H01L2224/92247 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/15192 , H01L2924/15322 , H01L2924/181 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2224/37099 , H01L2224/45099 , H01L2224/32245 , H01L2224/48247 , H01L2924/00
摘要： A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal.
摘要翻译：半导体器件封装包括具有第一和第二相对表面的衬底。芯片的第一表面耦合到衬底的第二表面，并且导电子端子的第一表面与管芯的电接触电耦合并物理耦合到衬底的第二表面。模具化合物封装模具和子端子的大部分。在实施方式中，模具化合物的第一表面耦合到基底的第二表面，并且与模制化合物的第一表面相对的模具化合物的第二表面与子端子的与第一表面相对的第二表面齐平子终端。在实现中，子端子包括具有垂直于衬底的最长长度的最长长度的柱。在实施中，导电销耦合到子端子的第二表面。

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